Startup launches analog IP from digital tools

Startup launches analog IP from digital tools

Technology News |
By Peter Clarke

The advantage of the approach is that because the functions are designed digitally time-to-market can be shorter and IP can be more easily ported to alternative process nodes or layer counts.

The company has launched a series of phase-locked loop (PLL) delay-locked loop (DLL) and low-voltage drop out (LDO) regulator generators.

It is not clear how the circuits compare with similar analog implementations in terms of performance, power consumption or area but the company claims that since its formation in April 2014 it has produced working silicon with multiple customers. These include semiconductor and systems companies working in artificial intelligence, networking, and FPGAs.

The PLL generator is available in TSMC 28nm HPC and Globalfoundries 14nm LPP process nodes. Meanwhile several FinFET process nodes are being prepared. The DLLs are designed to be robust against environmental and process variations and occupy 10,000 gates independent of the process technology while meeting a wide range of specifications, Movellus said.

The IP generators combine proprietary analog circuit architectures (RTL) with add-on software products that expand digital synthesis, static timing analysis, and place and route tools to create digital implementations of analog functions, Movellus said.

Next: Mythic experience

Fabless chip company Mythic Inc. (Austin, Texas) has experience of Movellus’ tools and IP. Founded in 2012 as Isocline Engineer Corp., Mythic is adopting a “processing-in-memory” approach to neural network implementation.

“Mythic delivers AI that performs hybrid digital/analog calculations inside flash arrays, resulting in orders of magnitude increase in efficiency,” said David Fick, CTO of Mythic. “The Movellus PLL generator has unique IP and software technology that expands existing digital tools to enable them to automatically generate PLLs, eliminating manual analog design methods.” Fick continued: “Their generator allowed us to focus on designing our SoC without worrying about any schedule slips due to late manual analog customizations needed to meet our goals. For example, when we needed to push a metal stack change, Movellus was able to provide a correct IP in a matter of hours.”

“By expanding existing digital design tools to create functionality previously only achievable in analog design, Movellus dramatically improves efficiency and reduces development and verification time by months,” said Muhammad Faisal, co-founder and CEO of Movellus, in a statement.

“I invested in Movellus after watching Muhammad and his team cross the critical hurdle of proving their technology in silicon with customers,” said Jim Hogan, managing partner at Vista Ventures.

Prior to founding Movellus Faisal held positions at PMC-Sierra and Intel. The management team also includes Jeffrey Fredenburg, co-founder and vice president of engineering, who leads the development of Movellus analog generator technology. The company’s chief operating officer is Saeid Ghafouri who joined Movellus having held executive positions at CoWare, Magma Design Automation, interHDL, Synopsys, Silicon Architect, and Cadence.

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