Startup looks to  IoT building blocks to shrink wearable technology

Startup looks to IoT building blocks to shrink wearable technology

Technology News |
By Wisse Hettinga

Silicon interposers used to be exotic technology, but they have become more common as fabrication practices have improved. It was used in high-end FPGA solutions like Xilinx’s Virtex-7 2000T where it delivered 10,000 connections between multiple die in a 2.5D architecture. Altera used a slightly different approach to link its high-speed serial interfaces to the FPGA fabric.

Figure 1: The tiny zGlue chip consists of a programmable silicon interposer fabric with multiple dies mount on top.

Silicon interposer system design tends to be less complex that an SoC design, but it is still a challenge. Up until now it hasn’t put the technology into the same realm as PCB design, but a company called zGlue is looking to change this—at least on a small scale.

zGlue has developed a programmable silicon interposer fabric that targets compact applications (e.g., wearable tech) that includes applications such as medical devices. It allows developers to combine die onto the fabric, resulting in a much smaller compact form factor.

The programmability of the underlying structure speeds the implementation process allowing chips to be delivered in as little as eight weeks while reducing the form factor by a factor of 10.

The zGlue interposer comes in one size at this point, but it can be used for any number of die that will fit on it. Developers can provide their own and work with zGlue to incorporate them into a chip, or they can take advantage of BGA “chiplets” that are die already approved by zGlue (see figure 2).

Figure 2: The zGlue architecture is built around the programmable silicon interposer fabric, but it also includes system and power management.

These include a range of sensors, microcontrollers, memory, and even RF technology like Bluetooth or cellular chiplets. The hybrid memory is used for configuration data, system test support, as well as secure key storage. Memory can also be supplied as a chiplet or as part of other devices like the microcontroller chiplets.

The ZiP platform can employ a number of analog and digital ports—up to 20 of each.

The system also comes with zGlue’s system and power management support. The power management support allows operation with a range of batteries, including lithium and NiCads, as well as low-voltage supplies. Systems have built-in voltage regulators. Eventually gGlue will have a zGlue ZiPlet Store where developers can pick and choose chiplets.

The current configurations provide a working area up to 48mm2 and 20 I/O pins. Standard external interfaces include I2C, SPI, UART, and GPIO. Analog/RF connections up to 2.4 GHz are supported. The interconnect fabric supports up to 3 K connections.

At this point zGlue handles most of the system configuration versus using an FPGA- or PCB-style layout tool. Developers typically come to zGlue with a block diagram or an existing PCB layout that will be converted into a single chip.

It is possible to perform similar tricks found in PCB designs — such as laying out larger spaces for a chiplet — so that larger, typically higher-capacity or -performance chiplets can be utilized in additional products. This is a common methodology when companies need to deliver a range of products with increasing levels of functionality, capacity, or performance.

zGlue’s platform is not a fit for all compact embedded applications, but it can be a significant advantage for those where small, custom configurations are needed. It is significantly less costly than creating a custom SoC while providing similar flexibility when the appropriate chiplets are available.

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