Startup offers technologies for power-constrained devices
Low power is an important feature in portable, battery-operated devices in today’s technologies and as we progress towards such systems in which wearables, 5G smart phones, and energy harvesting become ubiquitous, low power will be an absolute necessity.
TransSiP, a company with an extensive patent portfolio, has grown an extensive innovation in More-than-Moore (MtM) technology. MtM is the aspect of microelectronic products which complements the digital part of integrated systems. This approach enables the functionalities of a product that are not digital-related – and although it will not enable scaling according to “Moore’s Law”, the unique capabilities of this effort will enable migration from system board-level into the System-in-Package (SiP) or onto the chip (SoC).
TransSiP has developed advanced 3D heterogeneous, meaning active and passive, embedded System-in-Package innovations. The use of micro-metamaterials in their semiconductor packaging technology along with unique DC/DC conversion system architectures for use in noise-sensitive systems achieve the goal of extending the battery life in wearables and IoT microsystems.
Their recent introduction of their JC-PFM DC-DC converter chipset designed with a new concept in switched-mode DC-DC power conversion. This architecture consists of an integrated micro DC-DC converter and Harmony SNJ conditioner.
This family of devices integrates all the components needed to provide output voltages ranging from 1.0V to about 4.0V (±2.0%, 0.1V step increments) at 50/200mA with up to 93% conversion efficiency at full load and over 80 percent in power saving mode in two microLGA packages.
Applications that will greatly benefit from this technology include spread-spectrum wireless communications (WiFi, BLE, ZigBee), GPS/GNSS navigation/positioning, and other standby mode functions in remote, portable, wearable, and IoT devices.
Until now switched-mode as well as highly efficient pulse-frequency modulation (PFM) type DC-DC converters have been avoided in designs of power-constrained portable/wearable, remote and IoT systems due to the chaotic nature of switching noise on the output supply bias. Depending on the DC voltage regulation strategy employed, supply bias noise takes the form of periodic oscillations (“ripple” voltage), random voltage spikes (“transients” or “spurious” noise), and/or timing shifts (“jitter”) which can degrade the performance and stability of downstream noise-sensitive circuitry.
TransSiP’s patent-pending JC jitter conditioning technology and JC-PFM DC-DC converter are based on TransSiP’s discovery that dislocations in timing of switched-mode DC-DC conversion switching noise, or “switching noise jitter” (“SNJ”) become the dominant factor in downstream system performance once the amplitude of switching frequency noise components is attenuated.
The presence of SNJ means performance of noise-sensitive circuitry such as spread-spectrum communications transceivers, GNSS/GPS receivers, ADCs, or precision clocks will be sub-optimal or degraded if filtering focuses only on switching noise amplitude.
With these designs of high level of integration and small (max. 2.6mm x 2.2mm) size, the JC-PFM DC-DC converter is able to reduce board footprint by eliminating the need for discrete outboard components normally required in filtering switched-mode DC-DC power supplies, but enables potentially significant increases in system autonomy. The combined broadband attenuator and jitter conditioner in the Harmony component have no quiescent current draw, and conversion efficiencies at power saving modes where power-constrained systems spend most of their time are close to 80%- compared to 5% or less with the linear regulators commonly used in noise-sensitive applications today.
Availability to circuit designers will be in 4Q2016.
Steve Taranovich is the editor-in-chief of EE Times’ Planet Analog website where this article first appeared.
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Visit EDN for a more detailed technical look at this technology.
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