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Startup plans 4k RISC-V cores on 7nm chip

Technology News |
By Peter Clarke

The company has said it now wants to create energy efficient computing chips for artificial intelligence and machine learning using the RISC-V instruction set.

During his presentation at the 7th RISC-V workshop held in Milpitas, California, entitled ‘Industrial strength high-performance RISC-V processors for energy-efficient computing’, Ditzel said his company would be producing a supercomputer-on-a-chip made in 7nm CMOS process technology.

This chip would include two types of processor: the performance-oriented ET-Maxion 64-bit RISC-V core and the energy efficiency oriented ET-Minion 64-bit RISC-V core each with a vector floating-point unit. The advanced manufacturing process will allow 16 ET-Maxions to sit alongside 4096 ET-Minions.

Ditzel, a chip industry veteran well-known as a chip designer at Intel and Sun Microsystems and as founder of code-morphing startup Transmeta, also said the company would pursue both a product and an IP licensing business model. As well as selling its AI supercomputer chip, the company will license its ET-Maxion and ET-Minion cores to help proliferate the RISC-V architecture, Ditzel said.

Next: Western Digital invests


During his keynote at the RISC-V Workshop Martin Fink, CTO of Western Digital said his company had made a strategic investment in Esperanto. Western Digital intends to transition its own consumption of processors – over a billion cores per year – to RISC-V.

“Esperanto’s goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications which will drive computing innovation for the next decade,” said Ditzel. “By designing in leading-edge 7nm CMOS and with the simplicity of the RISC-V architecture, we can fit over four thousand full 64-bit cores each with vector accelerators on a single chip. By basing our chip on RISC-V we can take advantage of the growing software base of operating systems, compilers and applications. RISC-V is so simple and extensible that we can deliver world class TeraFlop levels of computing without needing to resort to proprietary instruction sets, thereby greatly increasing software availability.”

Earlier in his career, Ditzel helped launch the RISC processor movement when he co-authored ‘The Case for the Reduced Instruction Set Computer’ with U.C. Berkeley computer science professor David A. Patterson.

Related links and articles:

www.esperanto.ai

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