Subthreshold design at MCU-scale yields 10x energy efficiency
Sub-threshold design isn’t new, explains Mike Salas, the company’s Vice President of Marketing, dating as far back as the 1970s when Swiss watchmakers would operate select transistors in the sub-threshold regime to increase battery time.
But it was never easy, he concedes, and it is only through arduous academic research to which Ambiq Micro’s founders contributed that sub-threshold design could finally be used on a mass scale to gain absolute efficiency across millions of transistors.
The company Subthreshold Power Optimized Technology (“SPOT”) platform operates transistors at subthreshold voltages (less than 0.5V), rather than using transistors that are turned all the way “on” at 1.8V. It uses the leakage current of “off’ transistors to compute in both digital and analog domains.
In essence, because sub-threshold designs operate way below the typical 1.8V voltage for which today’s industry-standard CMOS transistors are characterised, they are far more susceptible to process and environmental variation than super-threshold designs.
In a whitepaper titled “Sub-Threshold Design – A Revolutionary Approach to Eliminating Power”, the company also highlights the effects of temperature variations on the threshold voltage Vth and its implications on a very faint current that varies exponentially in response to changing voltages.
For all these reasons, the company had to develop proprietary compensation and reading circuits sensitive enough to pick-up nano-amp or even pico-amp variations.
“Working on sub-threshold designs, we realized that the traditional models from foundries are not correct, at least on the low-voltage side”, said Salas. “We had to come up with a new testing methodology to measure the currents, then we designed new cell libraries and the necessary peripheral circuits”.
The patented SPOT platform, implemented in an industry-standard CMOS process, encompasses a design methodology with a dedicated cell library that could be used through a standard EDA design flow. The premium in silicon, versus traditional solutions, represents about 5% of extra die area, but the power savings are tremendous.
So much so that when asked why Ambiq Micro wouldn’t design a chip around an ARM Cortex-M0+ core to consume even less power, Salas just answered: “Because we don’t pay so much the power penalty as our competitors, we decided that we could afford a more powerful solution with the M4F, to execute more powerful algorithms and faster for IoT’s typical sensor data fusion applications”.
“We have such an advantage that we don’t have to make a decision between optimizing either the sleep mode or the active mode, we optimize both modes simultaneously while getting the best performance, without any compromise in any direction”.
“Of course, we could play the same old tricks as our competitors for power conservation, but it is not really necessary, because our current flow is so much lower than anybody else’s” Salas added.
“So now we can walk to a customer, and by redesigning their wearable device with our solution, they suddenly expand the battery life from days or weeks to months or years. Alternatively, on the same battery budget, they can decide to add more features and functions, or on the contrary reduce the battery”.
Because the SPOT platform could be applicable to just any design, it could well find its way into larger chips, though it is not Ambiq Micro’s current focus.
“We have had many companies approach us to license the IP but we have not gone that path yet”, told us Salas.
“We’ll continue to focus on the wearable/IoT market, since there is still a lot of innovation to be had in that field. As for larger chips, we can’t do everything, so we have chosen a close set of partners so they can implement our technology around our chips”, Salas continued, hinting at some partnership announcements around mid-2015.
The Apollo MCUs consume an industry-leading 30µA/MHz when executing instructions from flash and feature average sleep mode currents as low as 100nA. They operate at up to 24MHz and are available with up to 512kB of flash and 64kB of RAM to accommodate radio and sensor overhead in addition to application code.
Communication with sensors, radios, other peripherals and an optional host processor is implemented via I2C/SPI ports and a UART. On-chip resources include a 10 bit, 13-channel, 1MS/s ADC and a temperature sensor with ±2ºC accuracy. Two compact packaging options are available – a 64-pin, 4.5×4.5mm BGA package with 50 GPIO and a further size-optimized 2.4×2.77mm, 42-pin CSP with 27 GPIO.
The chips are sampling to selected customers now, with volume production planned in the spring of 2015.
Visit Ambiq Micro at www.ambiqmicro.com
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