Successful first silicon of Raven open-source RISC-V MCU

Successful first silicon of Raven open-source RISC-V MCU

By eeNews Europe

The open-source semiconductor project moved from design start to tape-out in under three months using Efabless design flow based on open-source tools. The mixed-signal SoC, named Raven, has been based on the community developed ultra-low power PicoRV32 RISC-V core. Efabless bench-tested the Raven at 100MHz, and based on simulations the design should be able to operate at up to 150MHz.

Raven’s open-source top-level design utilises X-FAB proprietary analogue IP and is created with an open-source design flow. This hybrid technique allows open innovation, while protecting proprietary IP.

Efabless and X-FAB chose X-FAB’s high-reliability XH018 process for Raven. The flexible 180nm 6-metal process has a range of options including a low power option, on-chip isolation for high voltages, and high-temperature flash memory. X-FAB’s XH018 process also meets automotive quality requirements.

Raven is available from the Efabless marketplace as a reference design without license fee.

For companies that want to learn how to get started with open-source IP semiconductor design, X-FAB provides a series of free webinars including “Handling of Complex & Diverse IC Designs Made Easier”, “Design Robustness”, and “IC Lifetime Calculation Made Easy”. Design kits and PDKs for open source IP designs are available.

More information

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