SureCore offers SRAM IP customization
The approach can prioritize power optimization over speed and area and covers multiple read/write ports, ultra-low leakage retention modes, low dynamic power, near-threshold operation, write masking and BIST/DFT support.
The SureCore service develops memory variants including SRAM and register files based on either standard foundry or custom bit cells, the latter capable of delivering ultra-low operating voltages, improved leakage characteristics and improved performance.
SureCore offers smart-assist circuitry for near-threshold operation across process and temperature extremes, traditionally a problem area for SRAMs.
“Today’s emerging markets aren’t playing by yesterday’s rules and SoC architects developing cutting edge low-power devices can no longer make do with standard memory IP,” said Eric Gunn, SureCore chief operating officer.
“A number of companies have come to us with ultra-low, application-specific power and performance targets that demand “out-of-the-box” thinking to achieve record-setting energy efficiency,” said SureCore CEO, Paul Wells.
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