sureCore tapes-out low power SRAM IP demonstrator chip
The device will validate the benefits of sureCore’s patented array control and sensing scheme, which lowers active power consumption to deliver greater than 50% power savings compared to current offerings in the same process.
sureCore’s energy-efficient SRAM IP memory was designed through a combination of detailed analysis and the use of advanced statistical models. In post layout simulations the memory showed 75% less power for read cycles and 50% for write cycles. In addition, the technology promises improved leakage performance saving between 20% and 40% depending on operating corner.
Paul Wells, sureCore CEO, said: "This is a major milestone for the company – the demonstrator device will allow us to take the next steps commercially. Although it is implemented in an FD-SOI process, the innovations developed by sureCore are not process specific and will map to both bulk CMOS and FinFET technologies. We are currently working closely with partners to implement this in 40 nm and 28 nm bulk CMOS."
Duncan Bremner, sureCore CTO, added: "Silicon proven technology is the real measure of an IP company. The engineering team have done a terrific job and have demonstrated that a return to fundamental, rigorous engineering principles and systems analysis has resulted in lower, world beating power consumption for SRAM dependent System on Chip (SoC) solutions."
Horacio Mendez, Executive Director of the SOI Industry Consortium, said: "sureCore is solving a critical problem for SoCs: power reduction for the memory components. Over the last several generations of System-on-Chip products, the memory blocks have limited the ability to reduce power and keep pace with Moore’s law. Through its FD-SOI implementation, sureCore offers a practical solution to this important problem."
Visit sureCore at www.sure-core.com
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