sureCore teams with Sarcina to package cryo silicon
sureCore in the UK has teamed up with US packaging expert Sarcina Technology to develop a custom package for cryogenic silicon chips.
This follows the successful evaluation of test chips in both 180 nm and 22nm process nodes for memory IP in quantum computing.
“This represents another critical step in our programme to make Cryo-CMOS available for the Quantum Computing (QC) ecosystem. Our CryoMem range of memory IP is silicon proven in addition to validating our library recharacterization service,” said Paul Wells, CEO of sureCore.
sureCore to license 22FDX CryoMem IP for quantum computing
“We have developed a reputation as the “go-to” design expert for companies needing to push the boundaries of current packaging technology. Whether this be for complex multi-chip 3D solutions, or, as in this case, for extreme low temperature operation, our experience and know-how allowed us to develop a custom BGA package specially for cryogenic temperatures,” said Larry Zu, CEO of Sarcina.
sureCore used its ultra-low power memory design skills to create embedded SRAM memory as an essential building block for any digital sub-system, that is capable of operating from 77K (-196°C) down to the near absolute zero temperatures needed by quantum computing. Both standard cell and IO cell libraries have also been re-characterised for operation at cryogenic temperatures thereby enabling an industry standard RTL to GDSII physical design flow to be readily adopted.
A key barrier to quantum scaling is being able to collocate ever increasingly complex control electronics close to the qubits that must be housed at cryogenic temperatures in a cryostat. In doing so, it is essential that the control chip power consumption is kept as low as possible to ensure that excess heat is kept to a minimum so it does not cause additional thermal load on the cryostat.
Current quantum computer designs have the control electronics located outside the cryostat as modern semiconductor technology is only qualified to work down to -40°C. As the temperature is reduced close to absolute zero the operating characteristics of the transistors change markedly. Measuring, understanding and modelling this behavioural change over the past months showcases the potential to build interface chips that can control and monitor qubits at cryogenic temperatures.
At the moment, expensive bulky cabling connects room temperature control electronics to the qubits housed in the cryostat. Enabling developers to be able to exploit the fabless design paradigm and create their own custom cryogenic control SoCs, which can be housed with the qubits inside the cryostat, is key to scaling the technology.
“We are also offering a range of cryogenic design capabilities to help QC companies design the control/interface chips which need to be migrated into the cryostat alongside the qubits. Reliable, robust, cryo-ready chip packaging is a necessity in these harsh, low temperature environments and to ensure this we partnered with Sarcina whose specialist package design expertise is second to none,” said Wells.
The next step will be characterising the demonstrator chip at cryo temperatures to further refine and validate the models to help improve the performance.
www.surecore.com; www.sarcinatech.com
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