Survey shows continued decline in first-time-right IC design
A worldwide survey of 597 design verification engineers and executives has found a significant decline in first-time-right IC designs in 2024.
It shows that only 14 percent of IC designs prove correct at the first pass. This compares with about 26 percent in 2012 and 32 percent in 2012.
IC/ASIC spins required before production by percentage. Source: Wilson Research via Siemens.
The survey was commissioned by Siemens Digital Industries Software and conducted by the Wilson Research group. The study was global with participants drawn from North America, Europe including Turkey and Israel, India and East Asia in the following percentages 31, 26, 11, 29, respectively and 3 percent from other geographies.
The report highlights the increasing complexity of IC and ASIC design. Multifunctional integration of embedded processors and analog circuits alongside an increased emphasis on security and safety requirements.
While logical and functional design errors remain the leading type of flaw contributing to a design respin these percentages are stable or reducing compared with previous years’ surveys. What is rising is errors related to yield, reliability, safety and security.
The survey data shows that those projects that use formal verification and other advanced verification systems experience fewer design respins. However, debugging of verification scripts takes up most of the design verification engineers’ time.
Verification engineers are therefore in high demand. The ratio of verification engineers to design engineers can be 5: 1 in some demanding segments.
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