SuVolta to talk low power at ARM TechCon
On Oct. 25 Thompson will compare FinFET, SOI, and planar bulk technologies at the 22-nm node and below.SuVolta (Los Gatos, Calif.) recently announced its Deeply Depleted Channel (DDC) transistor technology and PowerShrink low-power CMOS platform, which the company claims reduces IC power consumption by 50 percent or more while maintaining circuit performance.
The novel DDC transistor structure enables reductions in both the supply voltage and of the transistor size to the sub-20nm node while maintaining compatibility with established fabs and design techniques, according to SuVolta.The technology would appear to have similar characteristics to fully-depleted silicon-on-insulator (FDSOI) without the extra cost of FDSOI wafers.
SuVolta is working with Fujitsu and other semiconductor companies to realize its technology in leading-edge manufacturing process technologies SuVolta, formed in 2005 under the name DSM Solutions Inc., is a member of the Silicon 60, EE Times’ list of emerging technology startups.
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