Swiss made open-source processor core ready for IoT
Open-source and collaborative development is now standard practise in the software world – Linux being an example. While there have been hardware efforts, such as OpenRISC and Opencores, open-source hardware has gained the most traction at the board level. Examples include Arduino and Raspberry Pi, for which the PCB designs are publicly available. However, the chips on which those boards are based have remained proprietary.
Now a team led by ETH Professor Luca Benini, has put into the public domain the full design of one of their microprocessor systems, a derivative of the PULP (Parallel ultra low power) project.
The 32-bit PULPino is designed for battery-powered devices with extremely low energy consumption. The arithmetic instructions are also open source: the scientists made the processor compatible with an open-source instruction set – RISC-V – developed at the University of California in Berkeley (see India prepares RISC-V processors).
PULPino is a simplified version of the more general PULP, in that it has a single processing element rather than a cluster of four processing elements and has simplified instruction and data RAMs and was implemented in FPGA in 2015. According to presentation materials (downloadable from www.pulp-platform.org) the PULPino core is called RI5CY and is a four-stage in-order pipeline implementation of RISC-V.
The core which is compared to a Cortex-M4 from ARM, has an instructions per cycle figure close to 1, support for the base integer instruction set (RV32I), compressed instructions (RV32C) and partial support for the multiplication instruction set extension (RV32M). It implements non-standard extensions for hardware loops, post-incrementing load and store instructions, ALU and MAC operations. To allow embedded operating systems such as FreeRTOS to run, a subset of the privileged specification is supported. When the core is idle, the platform can be put into a low power mode, where only a simple event unit is active and wakes up the core in case an event/interrupt arrives.
The PULP quad-core IC was subject of a tape-out in 28nm from Globalfoundries in November 2015 while the first PULPino implementation (called Imperio) taped out in January 2016 in 65nm CMOS from UMC. The PULPino platform is available for RTL simulation, for FPGA and SoC . It has full debug support on all targets and includes a port of FreeRTOS. Operating at a clock frequency of 400MHz and 1.2V the chip consumes 32.8mW.
The license to use PULPino will be “very liberal” and aligned with that of the lowRISC, another open-source processor in development, according to the presentation materials.
“In many recent examples of open-source hardware, usage is restricted by exclusive marketing rights and non-competition clauses,” said Professor Benini. “Our system, however, doesn’t have any strings attached when it comes to licensing.”
The team reckon PULPino could be used to drive smartwatches, sensors for monitoring physiological functions or sensors for the Internet of Things. PULPino is being used in other research projects in Swiss and European research institutions and at Cambridge University.
Professor Benini said that PULPino should also be of interest to small and medium sized companies (SMEs) in Europe who often cannot afford to develop application-specific circuits Development costs are reduced considerably with the open-source royalty-free design, which benefits SMEs as well as ETH, says Professor Benini.
Related links and articles:
News articles:
RISC-V: An Open Standard for SoCs
India prepares RISC-V processors
Cambridge Calling: The rise of the ARM clones
Android processor core is royalty free
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