Switcher peak current-mode control circuit optimization for automotive applications
Abstract
Switching above 1.7 MHz to avoid AM band interference, and fast load transient response, are now constant pressures in switch-mode power supplies used in automotive infotainment systems. Today’s multicore processors and system-on-a-chip (SOC) require core voltages, even below 1V, to be tightly regulated from an intermediate voltage of 2.5V to 6V. At the same time, power supply designers target high-switching frequencies, compact solutions and fast transient responses. This article studies design optimization in depth for peak current-mode control loops. This step-by-step design considers parametric variation, parasitic elements, as well as typical automotive requirements. A family of synchronous buck converter devices is used to demonstrate optimization.
Introduction
Today’s multicore processors and system-on-a-chip (SOC) require low, but tightly regulated core voltage supplies that react very quickly to transients. We provide a test case that requires a core voltage of 1.2V with overall accuracy of +/–3%, which includes the transient response. The load transient is specified as 0.5A to 2A within 400 ns. Additionally, the behavior during load transients is explained, relevant formulas are derived and applied to the example.
Circuit behavior during load transient
During load transient, the feedback loop takes finite time responding to the current demand. This causes a dip in the output voltage (Figure 1). The duration of this dip is known as the system response time, Tr. During this time the load current is the sum of both inductor and output capacitor currents. The output voltage dip cannot be avoided, but can be minimized to meet the specification.
All calculations provided assume the following definition:
- Io: load current
- Ic: current from output capacitor COUT
- IL: current from the inductor L
- Tr: loop response time
- VOUT: output voltage
Assuming the load step happens at time zero t = 0, and the parameters initial value are Io(0) = Io, IL(0) = 0, Ic(0) = Io and VOUT (0) = V0, this behavior can be explained using equations 1 – 3:
Equation 1 – 3 result in: 
which can be converted to equation 4:
With an inductor current and the output voltage being continuous functions at t = 0, integrating equation 4 results in equation 5:
The constant represents the output voltage V0 at t = 0 as
The voltage dip during the load step is ΔVOUT = VOUT – V0 (equation 6):
Equation 6 is a parabolic function and its minimum is when the derivative This gives the ΔVOUT minimum at t = Tr, or equation 7:
Equation 7 gives the difference between the lowest output voltage during load step and the initial voltage before the load step. The negative sign indicates that the output voltage drops below its initial level. The output voltage dip is proportional to the load step current, feedback loop response time, and is inversely proportional to the output capacitor value.
Optimizing transient response
The design goal is to minimize the output voltage dip of ΔVOUT min. This can be achieved by increasing the output capacitor and lowering the loop response time, Tr, which is a function of the crossover frequency, Fc, given in equation 8:
Equations 7 and 8 can be derived to (equation 9):
Two important parameters to be optimized are: 1) output capacitor, COUT, and; 2) crossover frequency, Fc. By increasing these two values, the output voltage dip can be minimized. However, because there is no ideal circuit, the output voltage dip can be minimized only to a certain level. An often limiting factor is the bandwidth of the error amplifier.
Overall loop transfer function
Following basic signal theory, the transfer function H(s) = VOUT/Vr, where Vo is the small signal output voltage and Vr is the return signal.
Where RL is the load resistance, ESR is the output capacitor series resistance, and COUT is the output capacitor (Figure 2):
Error amplifier gain
The total error amplifier gain depends on the open loop gain and compensation network. For an ideal transcondutance error amplifier, R0 is infinite and C0 is zero. This allows constant gain across an infinite bandwidth. However, a real transconductance error amplifier has a finite output resistance and a small capacitance. These values impact the error amplifier gain. As they often are not specified, they are calculated from the unity gain bandwidth.
The error amplifier is a transconductance amplifier with VSENSE input and VCOMP output. The error amplifier output current i is proportional to VSENSE and i = gm x VSENSE.
The error amplifier output voltage, VCOMP, is the output current i multiplied by the compensation network impedance Z formed by R3, C1 and C2. Also, the internal impedance, Z0, formed by R0 and C0 need to be taken into consideration (equation 14):
With that, the transconductance amplifier open loop transfer function can be calculated as (equation 15):
Equation 17 is a first order transfer function with DC gain of gm∙R0 and a pole at 1/(2πR0C0).
The error amplifier can be considered as ideal at low frequencies, but the bandwidth is limited due to this pole. Typical error amplifier bandwidth ranges from 3 to 5 MHz.
Transforming equation 15 into the frequency domain S = j2πF, the transconductance amplifier open loop transfer function is defined as (equation 16)
with an amplitude as in equation 17 and phase of Tan(Ø) = -2πFR0C0.
If the error amplifier unity gain bandwidth is specified, R0 and C0 can be calculated as in equation 18 & 19, assuming a unity gain bandwidth of 5 MHz. As 2πFR0C0≫1 at UGBW, the gain can be simplified to equation 17:
Equation 19 can be derived to calculate equation 18:
where gm is the specified transconductance and F is the UGBD.
Applying a calculation example with gm = 250 µA/V and UGBD = 5 MHz, C0 is calculated as C0 = (250µA/V)/2πx5MHz=7.9pF.
At unity gain bandwidth the phase is very close to –90º. For example, a first approximation is Ø = –89.9º and Tan(Ø) = –573. This gives:
and R0 = 2.3 MΩ. The very high output impedance will be neglected later on and, therefore, justifies the first order approximation.
Compensation impedance Z
Another factor of the error amplifier gain is the compensation network impedance that can be calculated as:
which can be resolved to equation 21:
The total error amplifier output impedance is the equivalent impedance of
which can be calculated as (equation 23):
The denominator of equation 21 is a second degree equation and can be factorized by making the right approximation. The compensation resistor, R3, is in the order of a few 10 KΩ, so R3 << R0. The compensation capacitor, C1, is in the order of a few nF, and the high-frequency decoupling capacitor, C2, is in the order of a few 10 pF, so C0 + C2 << C1. This approximation leads to equation 24:
The denominator discriminant = (R0C1)² – 4R0R3C1(C0 + C2) = R0C1(R0C1 – 4R3(C0 + C2)). Using the same approximation R0C1 >> 4R3(C0 + C2). The simplified discriminant is (R0C1)².
This results in the roots S1 = 0 and 
and a total approximated error amplifier output impedance of 
With that, all factors of the transfer function are described and the overall open loop transfer function given in equation 10 can be calculated as equation 25:
Calculating compensation values
After deriving the open loop transfer function, the right components for achieving the desired bandwidth and phase margin have to be calculated.
The error amplifier and power stage transconductances, Gm and gm, are specified in the device datasheet. The output capacitor, COUT, and inductor are calculated for achieving low-output ripple voltage at the switching frequency. Transforming equation 25 into the frequency domain and entering equation 13, the transfer function can be calculated as equation 26:
From this transfer function, we can clearly identify the DC gain as 
It also shows two dominant poles, 
and one dominant zero at 
To simplify the calculation, the following assumptions are made. The output capacitor is a low ESR ceramic of less than 5 mΩ and, therefore, is zero at a higher frequency. C2 is too small to decouple a high frequency, and also can be neglected. For an easier calculation of the crossover frequency Fc and phase margin ΔØ, the gain is simplified as equation 27:
The result is a gain of 
As the design goal is to achieve high crossover frequency, it can be assumed that 1≪(R3C1ω)² and 1≪(RLCoutω)². With this approximation the gain can be simplified to equation 28:
At the crossover frequency H is equal to 1, which leads to 
which can be converted to equation 29:
Calculating the phase of equation 25 results in equation 30:
For a stable design, the phase margin is targeted at > 45°. However, for a robust design, and taking the additional phase drop due to slope compensation into account, the compensation is set to reach Ø = -90° at the crossover frequency.
This is the case if atan(RLCoutω) is equal to atan(R3C1ω), which results to equation 31:
At higher frequencies, the output capacitor ESR creates a zero and results in increasing gain, which can introduce high-frequency noise. To compensate, a pole created by C2 can be used and should be set to near the ESR zero. In this case, C2 is set to equation 32:
Crossover frequency
The next step is to place the target crossover frequency. At lower frequencies the output stage is a voltage-controlled current source. The power stage gain Gm is constant at low frequencies. However, at higher frequency between one-sixth and two-thirds of the switching frequency, Gm has a pole of –20 db/decade and a phase at –90º. Therefore, the crossover frequency is limited. (The basic principle of current-mode control is explained in references 1, 2 and 3.) To account for this limitation, it is better to be conservative and choose the crossover frequency at one decade below half the switching frequency. With a 2 MHz switching frequency, the crossover is set to 100 KHz.
Calculation example
Following the theoretical description of the behavior above, the derived formulas are applied to an example. In our example we used TI’s TPS57114, an automotive catalog 2.95V to 6V input, 4A, 2 MHz synchronous step down SWIFT DC/DC converter [4].
The design targets for this example are to meet typical requirements for an automotive infotainment SoC.
Selecting switching frequency
To ensure that the switching frequency is well above the AM band while allowing high bandwidth and small components, 2 MHz is selected.
Output capacitor calculation
The output voltage ripple during steady state is caused by the ESR of the output capacitors, as well as the output capacitor size itself (equation 33).
To optimize the ripple performance and transient response, use a low series resistor (ESR) ceramic capacitor. Nevertheless, a realistic ESR of 2 mΩ results into 2 mV ripple. and the resulting ripple contribution of the output cap is only 3 mV. With a switching frequency of 2 MHz, COUT can be calculated as equation 34:
Beside the output voltage ripple, the transient response is another variable determining the output capacitor size. Applying formula 9 to this example, we get
To select the right output capacitor size, the larger numbers of equation 34 and equation 35 should be selected. In order to add some margin 5 x 22 µF are selected.
Calculating the compensation network
Using equation 29, the compensation resistor, R3, can be calculated as
A standard value of 18 k is selected. Equation 31 than leads to 
and a standard value of 1.8 nF is used.
Finally, the capacitor, C2, is calculated as 
The selected standard value is 10 pF. With these numbers, also used on the existing evaluation module, the frequency response can be measured. The crossover frequency is 80 kHz with a phase margin of ~45 degree.
With this crossover frequency, the resulting transient response can be calculated, using equation 7:
Applying a transient response to the circuit results into a transient response of ~30 mV (Figure 4).
Conclusion
Load transient response is a critical parameter for power supplies. To optimize this parameter, the behavior has been explained theoretically. After applying an example to the derived formulas, the resulting circuit has been build and characterized. The measured transient response and crossover frequency proves the step-by-step approach developed here.
References
“Venable Technical Paper#5, Current-Mode Control,” Venable Industries
Lloyd H. Dixon, Jr., “Current mode control of switching power supplies,” Texas instruments, 2001
“Hiroki SAKURAI, Yasuhiro SUGIMOTO, “Analysis and Design of aCurrent-Mode PWM Buck Converter Adopting the Output-Voltage IndependentSecond-Order Slope Compensation Scheme,” IEICE Trans. Fundamentals, Vol. E88-A, NO. 2, February 2005
"2.95 V to 6 V Input, 4-A Output, 2MHz, Synchronous Step Down Switcher (Rev. B),” TPS57114-Q1 datasheet (SLVSAH5B), Texas Instruments, April 2012.
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