Switching from C/C++ to FPGA hardware acceleration
The SDSoC environment provides a greatly simplified ASSP-like programming experience including an easy to use Eclipse integrated design environment (IDE) and a comprehensive development platform for heterogeneous Zynq All Programmable SoCs and MPSoCs deployment.
It comes complete with what the company claims to be the industry’s first C/C++ full-system optimizing compiler, supporting system level profiling, automated SW acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming.
During a demo at Embedded World, Xilinx showed eeNews Europe how easy it was for software engineers to switch from a software block to logic hardware acceleration in one click, with instant feedback on performance increase versus the software partition.
With the help of the built-in system level profiler, users can specify which functions should be accelerated in programmable logic and SDSoC instruments the C/C++ code to report software cycles and estimates for the data transfer as well as overall application speedup.
Used by systems and embedded software engineers, SDSoC provides an Eclipse IDE with C/C++ running on bare metal or operating systems such as Linux and FreeRTOS as its input. SDSoC enables the creation of complete heterogeneous multi-processing systems, including reuse of legacy HDL IP Blocks as C-callable libraries.
SDSoC supplies a full system optimizing compiler targeting both the ARM processors and the programmable logic on Xilinx’ MPSoCs. Without any knowledge about the underlying hardware, software teams can rapidly configure, generate macro and micro architectures with automated system connectivity generation optimized for performance, throughput, and latency.
Learn more about SDSoC at www.xilinx.com/sdsoc
Visit Xilinx at www.xilinx.com
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