Switching time reduction using poly-SiGe gate for p-Channel PowerTrench MOSFETs

Switching time reduction using poly-SiGe gate for p-Channel PowerTrench MOSFETs

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The properties of poly-Sil-xGex (pSiGe/pSiGeC) can be a favorable alternative to pSi in many applications. The main advantages associated are the lower transition temperature, process thermal budget, ability to dope heavily and easier to integrate with the existing Si devices.

The pSiGe/pSiGeC films can achieve lower resistivity than that in p-type pSi films when doped with boron. The lower P+ film resistivity is the consequence of substantial increases in boron activation and hole mobility which accompany with increases in Ge content. Considerably lower temperatures (~500°C) can be used to anneal boron-implanted pSil-xGex films, and lower boron implant doses can be used to obtain lower resistivities in pSil-xGex films, compared to pSi films. It is also reported that a significant improvement of thermal stability in doped B is achieved by increasing Ge fraction [2]. However, the resistivity of N+ doped pSil-xGex films with high Ge content (>45%) was reported to be higher than that of N+ pSi, due to reduced phosphorus activation [1].

In CMOS technologies, the pSiGe/pSiGeChas been expected as a promising alternative gate material due to its lower poly depletion effects (PDE) and boron penetration, and enhanced hole mobility by changing the gate workfunction for PMOS. Moreover in pSiGe/pSiGeCgate, the threshold voltage can be adjusted simply by varying the Ge content inside the films, which is much more convenient than the conventional ion implantation method. PSiGe/pSiGeC films have also been utilized for the low temperature (~550°C) TFT fabrications and the gate electrode of MOS transistors [3-7].

In this study, we have investigated the effect of the p-type pSiGe/pSiGeCgate on switching performance of power trench p-MOSFETs compared to the pSi gate MOSFETs. The deposition condition dependent surface morphology and other electrical properties of the fabricated MOSFETs with the pSi and pSiGe/pSiGeCgate electrode are also reported.

Experimental work

PSiGe/pSiGeCfilms were grown on 150 mm wafers by lowpressure chemical vapor deposition (LPCVD) method. SiH4 and 10% H2-diluted GeH4 were used as source gases. Germanium content is controlled by varying the GeH4 and SiH4 gas flows. Diborane (B2H6) gas is used as a p-type dopant source. For PSiGe/pSiGeC films, monomethylsilane (MMS) is used as carbon source.

The SiGe/SiGeC growth temperatures were in the range of 600 to 720°C in order to prevent surface roughening. Growth pressure of 10 torr was used. A 5700 Å thick, boron-doped pSiGe/pSiGeC/pSiGe/pSiGeCwas deposited on the silicon dioxide (SiO2) to serve as the gate dielectric material for the MOSFET. The pSiGe/pSiGeC film was dry plasma etched and recessed into the trench to pattern the gate electrode of the power trench MOSFET shown in Fig.1.

The etch was performed using a low-pressure and high-density plasma in a LAM Research single-wafer chamber using a mixture of sulfur hexafluoride (SF6) and chlorine (Cl2) diluted with an inert gas. An oxide breakthrough etch process precedes the two step pSiGe/pSiGeC etch process in the same etch chamber.

The oxide breakthrough step clears any native oxide formed over the pSiGe/pSiGeC film and help prevents hillock and nodule formation after the film is etched. During the first etch step, the bulk pSiGe/pSiGeC film is etched, until the optical end point system triggers the end of the 1st plasma etch.

The second; fixed time plasma etch step continues to remove the film to pattern the gate electrode to a desired depth inside the trench. Then the patterned film was subjected to BF2 implantation for P+ source formation and annealed in a furnace for source dopant activation. Subsequently, the titanium (Ti), titanium tungsten (TiW) and aluminum (Al) metals were deposited, silicided and etched to form source and gate contact regions.

Comparatively, pSi gate was manufactured by depositing pSi films on gate oxide in a furnace, P+ implanted with highest possible dosage for source and gate regions and then annealed to achieve lowest resistivity. All the other fabrication steps for forming the MOSFET device are identical to its pSiGe/pSiGeC /pSiGe/pSiGeC C gate counterpart. Fig.1 shows the cross-section of the fabricated power trench MOSFET structure with pSi/SiGe gate.

Fig.1 Cross-section of the p-channel MOSFET with pSiGe gate

The growth rates for the p-SiGe film were between 10 and 60 nm/min based on the process condition. The best process condition based on resistivity, uniformity, roughness and deposition rates is implemented to grow pSiGe/pSiGeC /pSiGe/pSiGeC gate for the MOSFET device.

The Ge and Boron contents (in atomic percent) of the p-SiGe films were estimated by secondary ion mass spectroscopy (SIMS) measurements. The film resistivities were measured using a four-point probe. The surface roughness, film thicknesses and cross-sectional studies were conducted using Atomic force microscopy (AFM) and Scanning electron microscopy (SEM) techniques. All the device parameters are tested using Eagle tester and the finished packaged die is bench tested for switching characteristics.

Results and Discussion

Surface Roughness

The deposition rates of pSiGe/pSiGeC increased from 10 to 60 nm/min with the increase in temperature, pressure and SiH4 gas flow rates in a LPCVD chamber. However, the film quality, roughness and uniformity showed deterioration, measured using AFM and cross-sectional SEM.

The roughness and film quality improved with the addition of monomethylsilane (MMS) gas. It is likely that the introduced carbon atoms could have reduced the pSiGe/pSiGeC grain boundaries and/or crystal lattice stress leading to smoother surface, which appears to be true in case of crystalline SiGeC [11].

The RMS roughness improved ~10x from 75nm to 7.5nm as shown by AFM profile in Fig.2. This is also approximately 1.5x improvement in roughness over PSi films.

Fig.2 Surface profiles of PSi (A), pSiGeC (B) and PSiGe (C)


The resistivity of pSiGe/pSiGeCfilm was reduced to 2m ohm-cm using boron dopant source (B2H6) compared to 5m ohm-cm for pSi films deposited in a furnace. In addition, process steps like P+ implant and anneal for pSiGe/pSiGeC films are not required resulting in cost improvement.

In conventional MOSFETs the charge carriers are depleted away from the pSi electrode and the silicon dioxide (SiO2) dielectric interface when the transistor is biased in inversion by applying a voltage between the gate electrode and the source (Vgs) of the transistor. Because of this charge carrier depletion, better known as the poly-depletion effect or PDE, a thin layer of the poly-Si in the vicinity of the dielectric becomes non-conductive, resulting in an apparent thickening of the dielectric when the device is biased in inversion mode.

The apparent thickening of the gate dielectric in turn causes degradation of the drain to source current density, which is a very important figure of merit for a transistor. pSiGe/pSiGeC has a smaller bandgap, compared to Si, lower activation temperature for the same percentage of activated dopants and lower diffusivity for certain dopants [8,9]. In particular, the presence of Ge allows for higher activated dopant concentrations without resorting to higher implantation doses [10].

As shown in Fig. 3, a 40% reduction in gate resistance (Rg) was recorded for devices with pSiGe/pSiGeC gate as compared to devices with pSi gate.

Fig.3 Gate resistance comparison between PSiGe and Psi

Average Rg for pSi gate was 6.25 ohms, while for the pSiGe/pSiGeC gate the value was 3.75 ohms. This is mainly attributed to the fact that more B atoms are incorporated and electrically activated in poly-SiGe than poly-Si, because the solid solubility limit of B in PSiGe/pSiGeC is higher than in pSi [2].

Another manifestation of the conventional pSi gate is that B atoms in pSi tend to diffuse through the gate oxides during the high thermal cycles involved in transistor fabrication. As evident in Fig. 4 below, the boron dopant profiles in the fabricated pSiGe/pSiGeC andpSi gate electrodes of the MOSFETs were compared using SIMS technique.

The dopant profile along pSi gate electrode shows the B concentration is decreasing at the surface due to out-diffusion, dropping sharply between the surface and 0.1µm and gradually increasing going deeper into the gate electrode. This phenomenon leads to degradation of the threshold voltage (Vth) stability in power MOSFETs using conventional pSi gate electrodes. However, the optimized pSiGe/pSiGeC gate electrode shows a uniform dopant profile with higher concentration along the length of the electrode, after annealing. Such a decrease in the diffusivity correspondsto the decrease in the local movement of B atoms from substitutional to interstitial sites, thus improving the thermal stability of B atoms.

Fig 4. SIMS profiles of B and Ge elements

Fig. 5, shows the comparative analysis of the Vth distribution for the conventional pSi gate and pSiGe/pSiGeC gate MOSFETs. pSiGe/pSiGeCgate MOSFETs have a lower Vth value of -1.8 V as compared to the pSi gate MOSFETs -1.5 V. Furthermore, the Vth distribution for the pSiGe/pSiGeCgate is tighter than pSi gate with a percentage variation of 5%, whereas the PSi samples show a variation of over 15%. This is clearly attributed to a more thermally stable B dopant incorporation into the pSiGe/pSiGeC gate electrode.

Fig.5 Vth comparison

The pSiGe/pSiGeC gate and pSi gate MOSFETs were packaged in a TO-220 3 lead discrete package and electrically characterized. A 60% improvement in switching performance was noticed for the pSiGe/pSiGeC gate MOSFETs over the conventional pSi gate counterpart.

The test circuitry and conditions have been omitted from the discussion for brevity. As evident from the summary in Fig. 6, the Toff for pSiGe/pSiGeC gate devices improved by 12 ns and Tfall was reduced by 10.7 ns. However, no improvement in Trise could be established, which was attributed to the high series resistance in the test circuit.

Better switching can make this P-channel power MOSFETs a strong contender in high efficiency power supply circuits and also reduce the cost of the power supply by eliminating the need for complex gate drive circuitry required for driving a N channel high side power MOSFET.

Fig.6 Switching performance comparison between pSiGe and pSi

Conclusion and Challenges

In summary, the electrical properties and compatibility with conventional Si processing of poly-SiGe makes it a potentially favorable alternative to poly-Si as the gate material for P channel power MOSFET. pSiGe/pSiGeC film doped with a similar dose of boron can achieve significantly lower resistivity than pSi films due to higher dopant incorporation and lower process thermal budget.

In these experiments we demonstrated a 40% reduction in Rg for the pSiGe/pSiGeC gate MOSFETs compared to their pSi counterparts. In addition, lower temperatures (~ 500°C) can be used to anneal boron-implanted pSiGe/pSiGeC films. Substitution of pSiGe/pSiGeC as the gate electrode material for P channel power MOSFET technology, presents additional advantages in terms of Vth stability and improvement in the device switching performance.

However, integrating pSiGe/pSiGeC gate in a commercial semiconductor manufacturing environment does presets challenges in terms of optimizing the film roughness/voids in filling smaller dimensions and plasma etching of these films. Further studies are needed to optimize the roughness and uniformity of the film through carbon and other dopant species to improve gate leakage performance of the devices.

Presence of Ge greatly increases the etch rate and the complexity of process control. The plasma etch has a very small process window for optimizing the etch rate and the optical end-point signal strength simultaneously in order to obtain a repeatable dry etch process. Controlling the pSiGe/pSiGeC recess into the trench to pattern the gate electrode also requires fine tuning the process in terms of reactive gas flow, RF power and pressure, while maintaining the integrity of the gate oxide.

About the author

Rohit Dixit is a product development engineer for Fairchild Semiconductor in Salt Lake City, USA, focusing on automotive products such as power trench MOSFET switches, linear analog regulators IC and electronic power steering modules.Dixit has worked as a research assistant at the Institute for Micro-Manufacturing at Louisiana Tech University and has developed organic n-channel and ambipolar field effect transistors. Dixit holds a BS in Electrical Engineering from Nagpur University in India and MS in microelectronics from Louisiana Tech University.


The author would like to acknowledge Fairchild Semiconductor, Fred Session and Qi Wang for the invaluable discussions throughout the course of these experiments.


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