Synopsys adds AI to its verification and test tools
Synopsys is adding reinforcement learning across all its chip design tools in a bid to boost the productivity of designers.
This builds on the DSO.ai tool, which has already been used on over 100 chip tapeouts.
Reinforcement learning (RL) is a very different type of machine learning, and has been used by Google to improve the chip design process for its tensor processing unit (TPU) chips, built on sub-10nm process technologies alongside Synopsys tools. Renesas and Samsung are already using the RL-based tools for their chip designs.
The addition to the Synopsys range are RL tools for verification and test. This is very different to the deep neural network (DNN) AI used for large language models such as ChatGPT.
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VSO.ai helps verification engineers reach coverage closure targets faster and find more bugs. The number of design state spaces in which a digital design can operate is nearly infinite, making it difficult for humans to check each of these spaces to validate that the design will function as intended. The regression process could run for days, eating up compute resources through thousands of tests, and this is where the expertise of verification engineers is vital. Often, the last mile closure ends up being very labour intensive, with manual analysis on huge amounts of data limited in yielding actionable insights.
VSO.ai examining the RTL to infer coverage while also highlighting areas where coverage is needed, saving substantial time. Renesas reports achieving up to 10x improvement in reducing functional coverage holes and up to 30% increase in IP verification productivity using AI-driven verification with Synopsys VCS functional verification solution, a part of Synopsys.ai.
RL has also been added to the TSO.ai tool for test pattern generation. There are three key metrics to consider when evaluating the results from an automatic test pattern generation (ATPG) tool: Defect coverage; pattern count, which correlates directly to testing cost; and runtime
Traditionally, optimizing for one of these metrics (typically by hand) negatively impacts the others. Someone who is new to ATPG may not have a strong sense of how to tweak the tool to generate the desired program results.
Conversely, someone with a lot of experience may have biases in the set up of the tool to achieve a certain result, which may not prove optimal for a new design. TSO.ai eliminates the tradeoffs, running multiple copies of Synopsys TestMAX ATPG advanced test solution to automate test program generation for enhanced defect coverage, fewer test patterns, and faster time to results.
One of the inherent advantages of using reinforcement learning for chip designs is that the tools learn from design to design and so get more effective.
Other developers of chip design tools, notable Cadence Design Systems, are also adding RL machine learning to their tools.
