Synopsys brings HAPS prototyping to the desktop

Synopsys brings HAPS prototyping to the desktop

By eeNews Europe

The system is designed for mid-range SoC prototyping and accelerates prototype bring-up and interaction with real-world I/O through built-in infrastructure to support GPIO, UARTs and a variety of SoC peripherals. The I/O flexibility is is intended to optimize connections for multi-FPGA design requirements. HAPS-80D also has a built-in debug infrastructure for HAPS GSV (Global State Visibility) with support for Synopsys’ Verdi SoC debug platform, as well as direct connection to a software debugger through Arm CoreSight, JTAG20 or MICTOR 38 interfaces.

HAPS-80D uses high-speed time-domain multiplexing (HSTDM) technology to provide high inter-FPGA communication performance with a capability of transferring design signals at 1.4Gbps single-ended. With automated partitioning and prototyping flow, HAPS-80D has the potential to scale with increasing design capacity and complexity. As part of the Synopsys Verification Continuum platform, HAPS-80D provides easy migration between Synopsys VCS simulation, ZeBu emulation, and HAPS prototyping solutions.

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