Synopsys, Cadence expand 3D Blox 2.0 support for chiplet designs

Synopsys, Cadence expand 3D Blox 2.0 support for chiplet designs

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By Nick Flaherty

Cadence Design Systems and Synopsys are expanding their support for TSMC’s latest 3D Blox chiplet specification.

New system prototyping flows based on the Cadence Integrity 3D-IC Platform support the TSMC 3Dblox 2.0 language extensions for developing and testing chiplet and multi-die designs.

The flows have been optimized for all of TSMC’s latest 3DFabric offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS) and System-on-Integrated-Chips (TSMC-SoIC) technologies.

At the same time the Synopsys Multi-Die System provides a unified exploration-to-signoff platform for full-stack designs using the 3Dblox 2.0 standard and 3DFabric technologies. The 3DIC Compiler tool in the flow allows a unified die/package exploration, co-design, and analysis platform.

The collaborations allow designers of AI, mobile, 5G, hyperscale computing and IoT 3D-IC designs can model system prototypes to accelerate design turnaround time with a common design language. The modular specification, developed with Ansys and Siemens EDA as well as Synopsys and Cadence, is designed to model, in one format, the key physical stacking and the logical connectivity information in 3D IC designs. It can be used for every aspect of 3D IC design, including physical implementation, timing verification, physical verification, electro-migration IR drop (EMIR) analysis, thermal analysis, and more.

Prototyping chiplet designs requires two different types of feasibility-checking methods across the various 3DFabric technologies—coarse-grained feasibility for thermal and EM-IR analysis, and fine-grained feasibility for die-to-die connections. 

Coarse-grained feasibility is enabled through a system-level tool integration with the Cadence Integrity 3D-IC Platform using the Voltus IC Power Integrity Solution and Celsius Thermal Solver across all TSMC’s latest 3DFabric configurations. 

Fine-grained feasibility is enabled through a silicon routing solution as well as joint collaboration on the development of a next-generation auto-router for 3DFabric technologies, which includes performance-boosting prototyping capabilities that support TSMC’s InFO and CoWoS offerings, enabled through the Integrity 3D-IC platform.

The platform combines system planning, implementation and system-level analysis in a single platform, and due to the shared infrastructure between Cadence 3D design and system analysis tools, customers can perform feasibility-checking much more efficiently. In addition, Cadence Allegro X packaging solutions have been enhanced with advanced InFO-specific design rule checking (DRC).

 The flows supporting the 3Dblox 2.0 standard provide chiplet mirroring, which lets engineers reuse chiplet module data, improving productivity and performance. In addition, the flows provide inter-chiplet DRC through the Cadence Pegasus Verification System, which helps designers create an inter-chiplet CAD layer for DRC automatically.

“With multiple packaging options available for implementation of multi-die designs, early prototyping and feasibility studies are becoming increasingly important,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Through our continued collaboration with Cadence and with the addition of the latest prototyping features that support the 3Dblox 2.0 standard, we’re enabling customers to leverage our comprehensive 3DFabric technologies and the Cadence flows to significantly improve 3D-IC design productivity and time to market.”

“The Cadence Integrity 3D-IC Platform is the unified solution that provides an efficient way for customers to leverage the new 3Dblox 2.0 prototyping capabilities to create leading-edge 3D-IC designs using TSMC’s 3DFabric technologies,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “By working closely with TSMC, customers adopting our new flows for use with 3Dblox 2.0 standard can accelerate the pace of innovation with next-generation multi-chiplet designs.”

At Synopsys, the integrated 3DIC Compiler system analysis capability allows co-optimization of thermal and power integrity aligned with 3Dblox 2.0 system prototyping, which helps to ensure design feasibility. Synopsys and Ansys continue to collaborate and deliver signoff accuracy for system-level effects with the integration of Synopsys 3DIC Compiler and Ansys multi-physics analysis technologies.

3DIC Compiler also interoperates with the Synopsys Test products to ensure volume test and quality.

“The ability to explore, analyze, and signoff multi-die system designs in a unified platform using a common standard like 3Dblox 2.0, along with the silicon proof of the Synopsys UCIe PHY IP on the TSMC N3E process, enables customers to accelerate system design from early architecture all the way to manufacturing,” said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys

The Cadence Integrity 3D-IC Platform includes Allegro X packaging technologies and is part of the company’s broader 3D-IC offering.;

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