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Synopsys drives 2nm analog IP, photonics with TSMC – update

Synopsys drives 2nm analog IP, photonics with TSMC – update

Technology News |
By Nick Flaherty

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Synopsys and TSMC are developing an end-to-end electronic and silicon photonics reference flow alongside developing analog IP on TSMC’s 2nm process technology.

New Foundation and Interface IP on the 2nm N2P process is in development, following silicon-proven IP on N3P. The first digital chips for AI built on 2nm have already taped out at TSMC.

The digital and analog design flows have been certified on TSMC N3P and N2 process technologies and have been successfully deployed by companies in AI, high-performance computing, and mobile designs.   

These digital and analog design flows use the Synopsys.ai EDA suite on the TSMC N3/N3P and N2 nodes. The Synopsys IC Validator enables full-chip physical signoff to handle the increasing complexity of physical verification rules and is now certified on TSMC N2 and N3P process technologies.

The PHY IP on N2 and N2P includes UCIe, HBM4/3e, 3DIO, PCIe 7.x/6.x, MIPI C/D-PHY and M-PHY, USB, DDR5 MR-DIMM, and LPDDR6/5x. The Foundation and Interface IP for N3P includes 224G Ethernet, UCIe, MIPI C/D-PHY and M-PHY, USB/DisplayPort and eUSB2, LPDDR5x, DDR5, and PCIe 6.x, with DDR5 MR-DIMM in development.

A new flow is available for TSMC N5 to N3E migration, adding to Synopsys’ established flows for TSMC N4P to N3E and N3E to N2 processes. In addition, interoperable process design kits (iPDKs) and Synopsys IC Validator physical verification runsets are available for design teams to efficiently transition designs to TSMC advanced process technologies.

The TSMC Compact Universal Photonic Engine (COUPE) technology is intended to meet the requirements for low-latency, power-efficient, and high-bandwidth AI and multi-die designs. 

COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods. TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

The collaboration on silicon photonics uses the Synopsys 3DIC Compiler and Photonics IC solution and TSMC’s COUPE technology for AI and multi-die designs. The flow spans photonic IC design with Synopsys OptoCompiler and integration with electrical ICs using Synopsys 3DIC Compiler and Ansys multiphysics analysis technologies.

Keysight, Synopsys, and Ansys have also introduced a new integrated radio frequency (RF) design migration flow from TSMC’s N16 process to its N6RF+ technology. Synopsys is currently looking to acquire Ansys.

“The advancements in Synopsys’ production-ready EDA flows and photonics integration with our 3DIC Compiler, which supports the 3Dblox standard, combined with a broad IP portfolio enable Synopsys and TSMC to help designers achieve the next level of innovation for their chip designs on TSMC’s advanced processes,” said Sanjay Bali, vice president of strategy and product management for the EDA Group at Synopsys.

“The deep trust we’ve built over decades of collaboration with TSMC has provided the industry with mission-critical EDA and IP solutions that deliver compelling quality-of-results and productivity gains with faster migration from node to node.”

“Our close collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys has enabled customers to address the most challenging design requirements, all at the leading edge of innovation from angstrom-scale devices to complex multi-die systems across a range of high-performance computing designs,” said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC.

https://www.synopsys.com/designware-ip.html

 

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