Synopsys launches ARC DSP for embedded AI

Synopsys launches ARC DSP for embedded AI

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By Nick Flaherty

Synopsys has launched smaller versions of its 512-bit VPX5 digital signal processing cor ebased around its configurable ARC processor technology

The 128bit VPX2 and 256bit VPX3 DSP IP are based on same VLIW/SIMD architecture, giving more flexibility for embedded applications, from AI to automotive.

The DesignWare VPX portfolio includes safety-enhanced implementations that meet random fault detection and systematic functional safety development flow requirements for full ISO 26262 compliance up to ASIL D in automotive designs.

The processors are supported by the MetaWare Development Toolkit with C/C++ compiler and associated libraries with vector length-agnostic programming to accelerate code development and portability.

“By expanding the ARC DSP processor portfolio with support for smaller vectors, Synopsys is enabling signal processing and AI in size, power, and thermally-constrained systems,” said Jim McGregor, Principal Analyst at Tirias Research. “In addition, the ultra-high floating-point performance and functional safety compliance of the VPX processors make them especially well-suited for the growing number of IoT applications like automotive, medical systems, and industrial automation. Synopsys’ ARC processors have been used by over 250 customers worldwide who collectively ship more than 2.5 billion ARC-based chips annually.”

Each VPX core contains a scalar execution unit and multiple vector units that support 8-bit, 16-bit and 32-bit SIMD computations. The VPX DSPs support half-, single-, and double-precision floating point formats, and up to three floating point pipelines are available in each VPX core.

A hardware accelerator support the specific functions used in linear and non-linear algebra functions to provide high-precision results. The VPX2 and 3 include enhancements to the instruction set architecture (ISA) and load/store bandwidth to deliver up to twice the performance of existing offerings for common DSP functions such as fast Fourier transforms (FFTs). 

“AI-enabled devices have an increasing need for specialized processors that can handle a variety of DSP and machine learning workloads with a high degree of energy efficiency,” said CL Chen, COO at Taiwanese AI chip designer Neuchips. “By expanding the ARC VPX processor family to support a range of vector lengths, Synopsys enables designers targeting a broader set of applications to implement high-performance signal processing in their designs.”

The safety-enhanced ARC VPX2FS and VPX3FS integrate hardware safety features including error correction code (ECC) protection for memories and interfaces, safety monitors and lockstep mechanisms that help designers achieve the most stringent levels of ISO 26262 ASIL B, ASIL C and ASIL D functional safety compliance.

The MetaWare compiler’s auto-vectorization feature transforms sequential code into vector operations for maximum throughput. Together with a robust set of software libraries that include DSP, machine learning and linear algebra functions, the MetaWare Development Toolkit delivers a comprehensive programming environment that accelerates time to optimum results and simplifies software portability.

“We continue to build on our industry leadership by expanding the DesignWare ARC processor family with the latest VPX DSP processors,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “Synopsys provides designers with a full range of scalable, software-compatible DSP IP solutions that address the varying performance, power and area requirements across a chip family.”  

The Synopsys DesignWare ARC VPX2 and VPX3 DSP Processor IP is scheduled to be available to lead customers in Q4 2021, with the VPX2FS and VPX3FS Processor IP in Q1 2022.

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