Synopsys looks to AI, 3D die for trillion transistor designs

Synopsys looks to AI, 3D die for trillion transistor designs

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By Nick Flaherty

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AI boosting the development of multi-die designs will be key to achieving trillion transistor devices says the CEO of design tool pioneer Synopsys.

“We see three major growth drivers for the industry, said Sassine Ghazi, Ghazi, who took over as CEO of Synopsys from founding CEO Aart de Geus in January this year.

“The rapid acceleration of AI is driving a massive improvement in productivity, not just in our space but in many end markets. Second is the proliferation of silicon. What going to power the AI advancements is the silicon,” he said at this year’s Synopsys User Group (SNUG) meeting which is celebrating its 35th anniversary.

“The third major driver is the increasing importance of software defined systems,” he said. “Its about the silicon and the system interacting to provide the best outcome for the various workloads running on the silicon.”

“To address the challenges form architecting the system to designing the silicon it requires a new approach and we cannot do it alone.”

This is the rationale behind the proposed $35bn acquisition of Ansys, particularly to add the physics modelling and digital twin technology to the Synopsys virtual development platform.

As part of this move Synopsys is introducing, a new AI-driven tool that is built natively into Synopsys 3DIC Compiler to provide a unified exploration-to-signoff platform and powered by fast integrated analysis engines. offers optimization for signal integrity, thermal integrity, and power-network design for chiplet and multidie design such as the Nvidia Blackwell GPU which is two die on a substrate with a coherent memory architecture..

Synopsys is now available to early adopters such as Nvidia and Intel.

Ghazi also highlighted a tool for early architecture exploration of multi-die systems, Synopsys Platform Architect – Multi-Die accelerates design timelines for the analysis of performance and power of 3D chip designs while accounting for the interdependencies between multiple dies. It allows systems architects to automate modeling, simulation, and analysis for early partitioning decisions, and helps customers avoid costly, late-stage changes and respins.

Additionally, he emphasized the importance of multi-die solutions, spotlighting Intel’s Pike Creek, the world’s first silicon-proven UCIe-connected and a result of collaboration between Intel, TSMC and Synopsys.

The chip, a collaboration between Intel, TSMC and Synopsys, includes an Intel UCIe IP die built on its Intel 3 process node and a Synopsys UCIe IP die built on the TSMC N3E process. Ghazi commented, “This is the future of the semiconductor industry: multiple fabs, multiple sets of industry standard UCIe IP, and modern EDA packaging solutions,” he said.

Synopsys also launched the latest version of its prototyping and emulation systems on the road to trillion transistor devices. “The HAPS 100 12 has increased capacity of 3x and reduced setup and can run interface IP at 400MHz,” said Ghazi, “and we have two hyperscalers using the HAPS 100 12. The Zebu EP2 (shown above) is built on HAPS 100 12 with 5.6bn gates in the emulation and prototyping system.”

Jensen Huang, CEO of Nvidia which used Synopsys tools from the very start in 1992, also spoke at SNUG to the changes that AI is driving. “This is the first time in 60 years that compute is being reinvented and how we build it will change profoundly in the next decade,” he said.



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