Synopsys looks to SoC digital twins with 30bn gates of emulation

Synopsys looks to SoC digital twins with 30bn gates of emulation

Technology News |
By Nick Flaherty

Synopsys has launched a hardware emulation system that can run digital twins of advanced system on chip (SoC) designs with up to 30bn gates.

The ZeBu Server 5 emulation system has 1.6x the gates of the previous generation with twice the throughput and half the power consumption. The system starts at 60 million gates, with up to 3.8 billion gates in a single rack. Up to 15 billion gates can be emulated in five connected racks and up to 30 billion gates with 10 racks. With power consumption of 6kW/billion gates, this is 22kW per rack or 220kW for the full system.

For the verification workloads of billion-gate designs and multi-die systems, performance, capacity and reliability are key to achieving faster software bring-up and hardware development. Digital twins play an important role, providing a digital replica of an electronics system used throughout the product lifecycle for software bring-up, power analysis and software/hardware validation.

AMD supplies the Virtex UltraScale+ VU19P FPGAs in the racks, each with 9m logic cells and PCI Express Gen4 interfaces to increase the throughput. These FPGAs are programmed with the working model of the chip in Verilog that will run firmware and even application software, testing out the latest chip designs for AI, mobile, automotive and networking applications.

“For billion-gate designs now required for compute-intensive applications, an exhaustive and accelerated debug process is only possible by using electronics digital twins,” said Hyundon Kim, principal engineer at Samsung. “With its high capacity and throughput, Synopsys ZeBu Server 5 provides an ideal solution to perform pre-silicon validation of our Exynos SoC products and enable early software bring-up and hardware development.”

Semiconductor and system companies can collaborate more closely with digital twins, ensuring that designs will work as intended and avoiding costly silicon respins. The ZeBu Server 5 is the first time there have been sufficient gates to model a digital twin of the latest chips, says Synopsys, enabling designers to speed up development of production-ready silicon. Availability on the cloud provides verification engineers the flexibility to scale up and down as their projects demand.

“Today’s software-driven systems—like the electronics found in an advanced car or VR headset—demand massive computing power for cutting-edge algorithms required to replicate complex scenarios in the real world or metaverse,” said Ravi Subramanian, GM of Synopsys Systems Design Group.

“Getting these products right means thoroughly testing the software running on your chip for over tens of billions of cycles on an emulation system before production. Synopsys’ ZeBu Server 5 delivers the highest performance emulation system in the world, with over 400 billion gates of chip capacity sold to customers all over the world, making it one of the most successful emulation products in the industry,” he said.

“While multi-die systems designs are helping to enable systems to meet the aggressive demands of compute-intensive applications, getting these highly complex systems to market quickly is challenging,” said Alex Starr, Corporate Fellow at AMD. “Synopsys ZeBu Server 5 was designed from the ground up to use the AMD Virtex UltraScale+ VU19P FPGAs to achieve fast emulation speeds at the demanding design capacity levels we see today. This enables us to meet the exacting market requirements for our most challenging designs.”


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