Synopsys renews layout tools for analogue, custom ICs in FinFET era

Synopsys renews layout tools for analogue, custom ICs in FinFET era

Technology News |
By Graham Prophet

The company observes that, while some observers had previously speculated that FinFET and 14/16 nm processes – and smaller – would remain the province of high-end digital designs alone; and that AMS and custom designs would “stick” at older process nodes, this is no more true now than it has ever been, and AMS design is migrating to FinFET processes.


This, according to the company’s David Reed, changes the detail work of analogue layout significantly. A single transistor, depending on the parametric performance required of it, becomes an array of fins – for example. However, Reed notes that despite the very different physical context, the intuitive understanding of circuit topology and floorplan that the analogue designer has, still transfers well to the FinFET era. In the immediately prior generations of custom layout tools, there had been a move to drive analogue layout with a more scripted, “logic-like” approach. This, Reed comments, has been a limited success and this new release of tools – Custom Compiler – in some ways represents a return to earlier techniques. Continuous, real-time parameter extraction and simulation guides the designer throughout the process.


Synopsys’ Custom Compiler is therefore pitched as “ Visually-Assisted Automation” with a number of point tools that are not full automation but are configured as “assistants”. Template Assistants help designers reuse existing custom layout know-how; In-Design Assistants reduce iterations with native design rule checks and parasitic extraction; Layout Assistants speed up layout tasks with user-guided placement and routing; and Co-Design Assistants unify custom and digital flow to accelerate mixed-signal IC design.


Custom Compiler, says the company, closes the FinFET productivity gap by shortening custom design tasks from days to hours. To bring new levels of productivity to FinFET layout, Synopsys has taken a fresh approach to custom design by developing visually-assisted automation technologies that speed up common design tasks, reduce iterations and enable reuse. Developed through close collaboration with leading customers, Custom Compiler is already in use for production work on the most advanced nodes and supported on FinFET process technologies by leading foundries.


Custom Compiler Assistants are productivity aids that build on the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup.

Layout Assistants speed layout with visually-guided automation of placement and routing. The router is ideal for connecting FinFET arrays or large-M factor transistors. It automatically clones connections and creates pin taps. The user simply guides the router with the mouse and it fills in the details automatically. The placer uses a new innovative approach to device placement. It allows the user to make successive refinements, offering placement choices but leaving the layout designer in full control of the results—without requiring any up-front textual constraint entry.

In-Design Assistants reduce design iterations by catching physical and electrical errors before signoff verification. Custom Compiler includes a built-in design rule checking (DRC) engine, which is extremely fast and can be active all the time. In addition to the DRC engine, electromigration checking, and resistance and capacitance extraction are all natively implemented in Custom Compiler. Custom Compiler’s extraction is based on Synopsys’ gold-standard StarRC engine.

Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Template Assistants actually learn from the work done with the Layout Assistant’s placer and router. They intelligently recognise circuits that are similar to ones that were already completed and enable users to apply the same placement and routing pattern as a template to the new circuits. Custom Compiler comes pre-loaded with a set of built-in templates for commonly used circuits, such as current mirrors, level shifters and differential pairs. The software “learns what works” and retains successful configurations for re-use, presetning them in a “gallery”.


Co-Design Assistants combine IC Compiler™ and Custom Compiler into a unified solution for custom and digital implementation. Users can freely move back and forth between Custom Compiler and IC Compiler, using the commands of each to successively refine their designs. With the Co-Design Assistants, IC Compiler users can perform full custom edits to their digital designs at any stage of implementation. Likewise, Custom Compiler users can use IC Compiler to implement digital blocks in their custom designs. The lossless, multi-roundtrip capability of the Co-Design Assistants ensures that all changes are synchronised across both the digital and custom databases.


Custom Compiler is based on the industry standard Open Access database. It provides an open environment spanning schematics, simulation analysis and layout. Unified with Synopsys’ circuit simulation, physical verification and digital implementation tools, Custom Compiler provides a comprehensive custom design solution.





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