Synopsys rolls ASIL-certified processor IP to ADAS designers

Synopsys rolls ASIL-certified processor IP to ADAS designers

Technology News |
By Christoph Hammerschmidt

Synopsys’ new “ARC EM Safety Island” DesignWare IP contains verified dual-core processors based on Synopsys’s ARC EM4 32-bit processor architecture that support safety criticality in two ways: This IP is already certified to meet ASIL D, the highest level in the risk classification scheme of the ISO 26262 safety standard. Its architecture contains integrated safety monitors as well as a lockstep mechanism, a second “shadow” processor that executes the same code as the main processor to rule out hardware faults. Other features adding safety to the system are multiple hardware safety functions, error correction code (ECC) technology as well as a programmable watchdog timer to detect system failures and runtime errors. This IP will be available initially for Synopsys’ EM4SI and EM5DSI virtual processors; in the second quarter the company plans to add the EM6 and EM7D cores.

ASIL D Ready Certified Dual-Core Lockstep Processors
with Integrated Safety Island

The new IP differs from earlier Synopsys safety packs in that it is supporting ASIL D which requires a lockstep mechanism. Existing safety packs lack this function.

The EM5D core support fixed-point DSP, vector and single-instruction / multiple data (SIMD) data processing. To increase performance in filter, TFT and other signal processing algorithms, the EM5D supports fractions, rounding, divisions, square root and fixed point calculations.


The ARC EM Safety Islands IP comes with comprehensive documentation that includes several features required to submit the system to ISO 26262 certification, such as FMEDA reports (Failure Modes, Effects and Diagnostic Analysis). Synopsys also provides an ASIL-D certified toolkit that facilitates and speeds design, debugging and optimization of ISO26262 compliant software for these processors. The company also claims that the ARC EM Safety Island IP has been designed to meet the footprint and safety requirements of a broad range of automotive applications including driver assistance systems, radar and sensor systems. “Eliminating single points of failure in safety-critical SoCs is a paramount issue to achieve ASIL D certification,” explained Wolfgang Ruf, product manager in the semiconductor business of certification institute SGS-TÜV Saar GmbH. “By using the verified and ASIL D certified ARC EM Safety Islands IP, developers can significantly reduce the design effort and the time to receive the ISO26262 certification for their automotive SoCs”.

The DesignWare ARC EM Safety Islands are configurable and extensible. Thus, application specific requirements with regard to performance, power consumption and chip area can be met.

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