MENU

Synopsys rolls lithography rule checker

Synopsys rolls lithography rule checker

New Products |
By eeNews Europe



Synopsys (Mountain View, CA) said the tool, Proteus LRC, provides comprehensive, process-window-aware checking features to identify locations in a chip design that are sensitive to process variations, thereby enabling corrective action to be taken prior to committing a design to manufacture. Proteus LRC is integrated into Synopsys’ Proteus mask synthesis flow and is targeted for use by optical proximity correction (OPC) and mask data preparation groups at semiconductor manufacturers, the company said.

Proteus LRC is designed to deliver the accuracy needed for 28-nm and below technology by using proven OPC models and rigorous first-principle models from embedded Sentaurus Lithography technology, Synopsys said. The Sentaurus Lithography technology embedded in Proteus LRC allows access to rigorous first-principle models for resist profiles and topography effects when identifying at-risk hotspots and determining the appropriate course of action, according to the company.

LRC includes double-patterning technology-specific checking functionality that provides error detection for each exposure and mask misalignment condition with a consolidated results viewing environment, Synopsys said. By taking advantage of Synopsys’ Proteus Pipeline Technology, Proteus LRC is able to efficiently handle the full-chip layout requirements of extreme ultraviolet (EUV) lithography, Synopsys said.

"We integrated Proteus LRC into the Proteus Mask Synthesis flow to allow semiconductor manufacturers to run the entire OPC flow efficiently on standard hardware resources," said Howard Ko, senior vice president and general manager of Synopsys’ Silicon Engineering Group, in a statement. "We also embedded Sentaurus lithography technology in Proteus LRC to provide OPC engineers with the ability to analyze critical hotspots with the highest level of accuracy."

Synopsys has also announced that it has extended its HAPS family of FPGA-based prototyping systems. The HAPS-600 series, the highest capacity extension of the HAPS family,extends FPGA-based prototyping capacity up to 81 million ASIC gates equivalent, Synopsys said. The HAPS-600 series, available immediately, is based on Xilinx Virtex-6 LX760 FPGA devices and offers performance up to 200 megahertz, according to Synopsys.

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News

Share:

Linked Articles
10s