Synopsys sees 100 commercial tape-outs using AI

Synopsys sees 100 commercial tape-outs using AI

Technology News |
By Nick Flaherty

Synopsys has seen the first 100 commercial tape-outs with its autonomous AI design tools.

Recent customers include STMicroelectronics and SK Hynix using reinforcement learning (RL) design tools on cloud and on-premise.

The Design Space Optimization AI tool can provide a 3x productivity increase, up to 25% lower total power and significant reduction in die size, with reduced use of overall resources, says Synopsys.

ST is using cloud-based versions of to generate extra momentum on the most intensive design phases. STMicroelectronics taped-out using Synopsys coupled with Synopsys Fusion Compiler and Synopsys IC Compiler II physical implementation tools.

“Using the Synopsys design system on Microsoft Azure, we increased PPA exploration productivity by more than 3x, allowing us fast implementation of a new Arm core, while exceeding power, performance and area goals,” said Philippe d’Audigier, system-on-chip hardware design director at STMicroelectronics.

“We look forward to accelerating our collaboration with Synopsys and Microsoft as we explore more opportunities for new industry-leading chip designs for key projects, including ST’s industrial MPUs.”

This comes as Siemens launched an AI-enabled verification suite and Cadence Design Systems has ben working with chip design customers on its Cerebrus AI-enabled design tool.

Traditional design space exploration has been a highly labour-intensive effort, typically requiring months of experimentation. Synopsys searches design spaces autonomously using RL to discover optimal PPA solutions, massively scaling the exploration of choices in chip design workflows and automating many basic tasks.

“Delivering high-performance, robust memory products at industry-leading volumes demands intensive optimization, which has traditionally been highly human intensive,” said Junhyun Chun, head of SoC (System on Chip) at SK hynix.

“Synopsys brings a huge amount of design team efficiency, giving our engineers more time to create differentiated features for our next generation of products. It’s also driving fantastic results as demonstrated in a recent project where delivered a 15% cell area reduction and a 5% die shrink.”

“AI’s ability to explore broader design spaces is accelerating our customers’ relentless drive towards better PPA and higher productivity with fewer engineering resources,” said Shankar Krishnamoorthy, GM for the EDA Group at Synopsys.

“We’ve monitored the first 100 commercial tape-outs by customers using Synopsys and the results are compelling. Whether they’re designing in the cloud, on-premise or a hybrid of the two, it’s clear that in every case, designers are seeing significant gains from optimized designs delivering better results and faster time-to-market. The cloud-side is particularly exciting as deploying Synopsys AI technology at scale in data centres ushers an exciting new era for designers everywhere.”

“Microsoft is committed to democratizing advanced chip design, so it was a natural move for us to host the Synopsys design system on Azure,” said Jean Boufarhat, corporate vice president, engineering, Azure Hardware and Infrastructure at Microsoft.

“With AI-powered chip design on Azure, companies can leverage cloud-scaling to boost productivity and optimize very large solution spaces like high-performance computing.”


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