Synopsys tools tape out 2nm chips at TSMC

Business news | September 25, 2023

By Nick Flaherty

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Synopsys says customers have taped out multiple chips on TSMC’s 2nm process as it certifies both analog and digital design flows.

Synopsys says the digital design flow for the TSMC 2nm N2 nanosheet process is achieving multiple tape-outs and the analog design flow adopted for several design starts. Samples are expected in 2024.

This is a significant move to have analog design flows and libraries available at the same time as digital on the leading process, especially with a shift from FINFET transistors to nanosheet, gate all around (GAA) devices. This requires new design and validation tools, which have been developed with Ansys and Keysight Technologies.

The design flows use the Synopsys.ai full-stack AI-driven EDA suite with interface IP in development to reduce integration risk and speed time. The technology is aimed at high performance computing PC, AI, and mobile SoCs.

AI-driven design technologies, including Synopsys DSO.ai, are being used to optimise the 2nm N2 designs to improve the power, performance, and area.

“High quality-of-results and faster time to market for advanced SoC designs are hallmarks of TSMC’s and Synopsys’ longstanding collaboration,” said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC.

“We work closely with our design ecosystem partners like Synopsys to deliver a full-spectrum of best-in-class solutions for TSMC’s most advanced process technologies, providing our mutual customers a clear advantage in meeting the silicon demands of high-performance applications, along with a proven path to rapidly migrate their designs from node to node.”

“The Synopsys digital and analog design flows for the TSMC N2 process represent a significant investment by Synopsys across the full EDA stack, helping designers jumpstart their N2 designs, differentiate their SoCs with increasingly better power, performance, and chip density, and accelerate their time to market,” said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. “Our close collaboration with TSMC through every generation of TSMC’s process technologies enables us to deliver unmatched EDA and IP solutions that customers need to innovate and strengthen their competitive advantage.”

The Synopsys analog flow enables efficient reuse of designs from node to node on TSMC advanced processes. As part of the certified EDA flows, Synopsys provides interoperable process design kits (iPDKs) and Synopsys IC Validator physical verification for full-chip physical signoff.

An RF design reference flow was developed with Ansys and Keysight for the TSMC N4P RF FinFET process with an interoperable iPDK that runs down to 2nm.

The analog design migration flow can be used across the N4P, N3E, and N2 process technologies. The analog design migration flow, part of the Synopsys Custom Design Family, includes a machine learning-based schematic and template-based layout migration solution to speed up overall analog design migration tasks.

The tools have integrated parasitic-aware, AI-driven optimization to help overcome the manual and iterative effort typically required to tune analog designs to meet all specifications. Using the flow, engineers can optimize their design in the new technology node while shaving weeks off engineering time and effort.

“Increased chip complexities, engineering resource constraints, and tighter delivery windows are driving companies to AI-driven solutions to help accelerate quality of results and time to results,” said Bali.

“Our collaboration with TSMC on the analog design migration flow for TSMC’s N4P, N3E, and N2 processes enables mutual customers to unlock massive productivity gains with efficient migration of their designs from node-to-node.”

The certified EDA flows are available now.

www.synopsys.com; www.tsmc.com