Synopsys updates IC place-&-route flagship; IC Compiler II

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By eeNews Europe

IC Compiler, Synopsys says, is the biggest single product in its overall offering: in looking to renew it, the question the company asked was, “what more [in P&R] can we do?”. Built from the ground up on a completely new, multi-threaded infrastructure, IC Compiler II introduces ultra-high-capacity design planning, unique clock-building technology and advanced global-analytical closure techniques. As a major step from the existing IC Compiler, the new tool will be offered in parallel; the existing suite will continue to be supported and developed. It will be most attractive to the leading-edge nodes; Sysnopsys says that its collaborators who have helped develop it have employed it at 28 nm and below, “…and one at 45 nm.” Users will migrate from IC compiler, “according to design need and at a time of their choosing.”

However, Synopsys sees many of its customers opting to stay at more mature process nodes, for longer, as the increased complexity of moving to a new node can result in a diminshing-returns effect. If market advantage cannot be so easily gained by technology progression, then the need for effective tools to, “get chips out” becomes more prominent.

The claim of 10-times faster throughput is based on separate speed-ups of 10x in design planning, 5x in implementation, and doubled capacity. This enables, Synopsys says, a more speculative approach to IC layout, with more freedom for designers and architects to try out design variants.

next; IC Compiler II structure

The new tool has been, “several years” in the making, the company says, and according to a spokesman, “We ended up rebuilding almost everything,” although some modules, for example the ZRoute component, have been re-used. IC Compiler II is a full featured place and route system centred on a new multi-threaded infrastructure, able to handle designs with more than 500 million instances. Exemplifying its “rethink, rebuild and reuse” development strategy, IC Compiler II relies on industry standard input and output formats, as well as familiar interfaces and process technology files, while introducing innovative design storage capability. It was architected from the outset with a full chip-level focus, deploying design planning capabilities that provide a 10-fold performance boost while consuming 5-times less (host system) memory. This enables designers to quickly evaluate many floor-planning alternatives to arrive at the right starting point for implementation. Block level functionality is driven by a new global analytical optimisation engine, a completely new clock generator and algorithmic capabilities in post route optimisation, which together enable enhanced quality of results (QoR) in area, timing and power. The “rethink” part of the process involved looking at how the tool handles timing, design hierarchy and clock generation, among other factors. A key component is an optimisation element called APS, that carries out “global analytical optimisation”. Placement and clock optimisation are melded into a single step. IC Compiler II also incorporates leading technologies used in IC Compiler, such as the conjugate-gradient placer and the ZRoute router.



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