Synopsys’ Verification Compiler spans complete verification flow for SoC
Native integration of simulation, static and formal verification, verification IP (VIP), debug, and coverage technologies into a single product boosts performance and productivity; advanced SoC debug capabilities build on the Verdi3 debug platform enhance debug efficiency. The methodology includes complete low power verification with native low power simulation, X-propagation simulation, next generation low power static checking and low power formal verification.
A broad portfolio of verification IP, including ARM AMBA 4 AXI and AMBA 5 CHI interconnect, Ethernet, MIPI, PCIe and more, are integrated with simulation and debug.
Verification Compiler is a product that Synopsys has structured for system on chip (SoC) verification technology and verification roadmaps. It is a complete portfolio of integrated verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure. Together these technologies offer a five-times performance improvement and a substantial increase in debug efficiency, enabling SoC design and verification teams to create a complete functional verification flow with a single product. The combination of next generation technologies, integrated flows and a unique concurrent verification licensing model enables Verification Compiler to deliver a claimed three-times gain productivity overall – directly addressing the growing SoC time to market challenge.
Advanced SoC development faces exponential growth in verification complexity, new power efficiency requirements, increasing software content and tougher time-to-market pressures. Achieving verification closure for these complex SoCs requires a broad set of technologies including advanced debug, static and formal verification, low-power verification, verification IP and coverage closure.
To address this challenging verification landscape, Verification Compiler features a comprehensive set of next-generation technologies, including formal verification, SoC connectivity checking, SoC-scale clock domain crossing (CDC) checking, X-propagation simulation, native low power simulation, and advanced verification planning and management. Verification Compiler also includes the entire portfolio of Synopsys’ verification IP, including the corresponding test suites, all integrated for advanced debug and high-performance simulation. By integrating these technologies in a single product, Verification Compiler enables SoC design and verification teams to better solve the growing technical and schedule challenges of SoC verification.
Verification Compiler addresses the capacity challenges of verifying complex SoCs with a next-generation static and formal verification technology that is 3X to 5X higher in performance and capacity compared to other solutions available today. This new technology includes formal property checking, low power static checking, CDC checks, SoC connectivity checks, advanced lint and sequential equivalence checking. Verification Compiler static and formal capabilities are fully compatible with the Synopsys Design Compiler® and Synopsys IC Compiler™ use model and flows.
Verification Compiler uses all of Verdi3’s latest debug technology including numerous innovative debug capabilities that offer substantially increased debug efficiency. These new capabilities include Interactive Testbench (UVM-aware) Debug, Transaction Debug, HW/SW Debug, Power-Aware Debug, and Protocol-Aware Debug, all built on a unified environment. Verification Compiler further adds substantial debug efficiency through the tight integration of these advanced debug capabilities with simulation, VIP, formal verification, and coverage.
Concurrent Verification
Verification Compiler license includes three independent, concurrent keys: one key for all static and formal technologies; one key for simulation-related technologies (including all VIP); and one key for all debug technologies. These three keys can be used concurrently by a single user to enhance individual productivity, or they can be used independently by different individuals in the same company. This flexibility enables design teams to simultaneously perform multiple verification functions, achieving dramatic verification productivity improvements.
Synopsys; www.synopsys.com
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