Synthesis tool for low power adiabatic logic shows 10,000x improvement
Researchers in the US and Japan have developed a synthesis tool for adiabatic logic that has 10,000 times the energy efficiency of current FinFET devices and nearly 50,000 times better performance than 40nm CMOS.
The research team used a digital logic process called Adiabatic Quantum-Flux-Parametron (AQFP). This technique uses alternating current rather than direct current with a clock and power rails. The alternating current acts as both the clock signal and the power supply, so that as the current switches directions, it signals the next time phase for processing.
The adiabatic logic can be used to reduce the power in transceivers with current silicon fabrication process technology, reducing the power consumption in data centres and supercomputers particularly.
“The significant amount of energy consumption has become a critical problem in modern society,” said Olivia Chen, assistant professor in the Institute of Advanced Sciences at Yokohama National University. “There is an urgent requirement for extremely energy-efficient computing technologies.”
The team developed an automatic synthesis framework to translate from high-level logic description to AQFP circuit netlist structures. This was used on 18 circuits, including 11 ISCAS-85 circuit benchmarks, 6 deep-learning accelerator components and a 32-bit RISC-V ALU. The synthesis results demonstrate the significant advantage of AQFP technology with a boost of 9,313×, 25,242× and 48,466× energy per operation compared to TSMC’s 12 nm FinFET and 28 nm and 40 nm CMOS process technologies. The ALU in 40nm consumed 1410 fJ, compared to 0.04 fJ for the AQFP adiabatic logic.
“This showed that AQFP can achieve a reduction in energy use by several orders of magnitude compared to traditional technologies,” she said.
Next: Synthesis framework for evaluation of adiabatic logic
The researchers proposed a top-down framework for computing decisions that can also analyse its own performance using adiabatic logic. To do this, they used logic synthesis to create a scheme that takes the high-level understanding of the processing and how much energy a system uses and dissipates. This is then described as an optimised map for each gate within the circuit model. From this, Chen and the research team can balance the estimation of power needed to process through the system and the energy that the system dissipates.
This approach also compensates for the cooling energy needed for superconducting technologies and reduces the energy dissipation by two orders of magnitude. “These results demonstrate the potential of AQFP technology and applications for large-scale, high-performance and energy-efficient computations,” said Chen.
The plan is now to develop a fully automated framework to generate the most efficient adiabatic logic circuit layout. “The synthesis results of AQFP circuits are highly promising in terms of energy-efficient and high-performance computing,” said Chen. “With the future advancing and maturity of AQFP fabrication technology, we anticipate broader applications ranging from space applications and large-scale computing facilities such as data centres.”
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