Synthetic current control drives efficiency in IoT infrastructure
The launch of a large family of multiphase power controllers and peripheral power stages is a significant move for Intersil, says Mark Downing Senior Vice President, Infrastructure and Industrial Power Products. “There’s a lot of data centre growth that’s driven by the growth in cloud services and the next wave is the Internet of Things with connected machines and over the next few years that will grow significantly,” he said.
“This means that infrastructure equipment is being pushed to the max in processing power and bandwidth and that drives some challenging requirements on the power side in efficiency but also to reduce board space – if we are occupying a substantial amount of the board with power that limits the processing and that’s a big push by customers. What we are describing really power the high power core voltages for processors and other high power FPGAs and ASICs in data centres, communications equipment, basestations, switches and routers. These are expensive development that have taken several years to get to this point so we wanted to make sure the solutions are broad in the market.
The enabler for this development is synthetic current control. “Synthetic current control with fast transient reduces the need for output capacitance that saves a lot of board area and cost,” he said. “This is a full digital control solution and what we mean by synthetic current control is the controller is estimating what the inductor will be a cycle ahead of when the current is being drawn from the processor. This then takes a feedback loop from the actual value and adjusts it, so it tracks each phase current with zero latency which is how we get the very fast transient current.”
“If you take 300A and divide it into six 50A phases you need to make sure its 50A give or take in each phase. One of the things this controller does very well is current balancing on the high frequency loads. If you had a load step of 10A to 100A sweeping up to 1MHz this device will maintain the current balance, and that’s what Intel’s test plan requires.”
This then provides the fast voltage scaling from the processor to the DC-DC converter in support of the different loads that the processor is dealing with. There are different control interfaces for different chipmakers, from Intel’s SVID to AMD’s SVI2 and the more general purpose AVBus interface for voltage scaling used by Broadcom and Qualcomm for its ARM-based servers as well as by IBM. The PMBus has been included on all the parts as the telemetry interface but it’s not fast enough for voltage scaling.
The family architecture (below) then provides digital controllers with the different interfaces, each with a separate power stage. “We set out to provide a complete solution – they don’t want to source a controller from one vendor and power stages from another as you eend up with finger pointing, so that’s why we came up with this platform,” said Downing.
For example, a seven phase controller would need seven of the power stages paired with the controller with outputs summed together to provide the high current rail. This alsoo helps improve efficiency.
“As it goes to higher current loads its can add more phases and as it drops you drop phases, so you are not wasting energy in unused phases,” he said. ”That can all be controlled automatically, you have a lot of configurability for over current protection points, overvoltage, how to respond to transients, that can be set in different registers and protected memory space, scaling from 10A to 450A. You can also use phase doublers to take the seven phase controller and make it 14 phase for 450A – some of the latest Broadcom SOCs are drawing over 300A and people like to have margin when they are designing their systems and the currents are only going up so we are futureproofing the device with that current.”
Thecompany has reference designs with Intel, AMD, Qualcom, Broadcom, Cavium, and is also ‘aligned’ with Xilinx and Intel’s Altera division on higher end FPGAs.
Packaging is also an important part of the development. The power stage runs 20% cooler from the higher efficiency and a thermal package that gives a 20deg advantage. The vertical trenchFETs are connected by a copper clip that feeds an exposed pad on the package to draw the heat out.
The controllers have an onboard ARM Cortex M0+ microcontroller and memory to store fault events, with registers controlling add drop phase, limit points, and this is a key part of a move to a graphical user interface. The PowerNavigator software was developed in Java with a power map that for each of the rails selects a device and the number of phases to support each of the loads in the system. This allows developers to experiment with different phases and add droplimits to optimise the operation of the power stage.
“We had a real time example where we went into a customer in Cupertino, reconfiguring memory running on 3 phases down to two phases and showed the transient performance,” he said.
This is just the start, says Downing. ““We believe this platform addresses those requirements very well as its scalable in output current, very efficient in energy and conversion and has a lot of flexibility, including the ability to tune it on the fly. We are just starting to tap the potential for digital power here – we have customers who reconfigure their systems in data centres in real time -this is not something as a standard operating procedure but it is comforting for them to know they can do it.”
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