System-in-Package EDA solution for homogeneous and heterogeneous chip integration
The solution consists of the SiP-id (System-in-Package – intelligent design) design kit, an enhanced reference flow including IC packaging and verification tools from Cadence, and a new methodology that aggregates the requirements of wafer-, package- and system-level design into a unified and automated flow. By deploying the SiP-id methodology, designers can reduce design iterations and greatly improve throughput as compared to existing advanced packaging EDA tools, reducing the time needed to design and verify ultra-complex SiP packages.
In a typical use case with high-pin-count dies, packaging engineers using SiP-id and the accompanying reference flow and methodology were able to reduce time from more than six hours to only 17 minutes, compared to existing tools with manual operation, claim the two companies.
Cadence – www.cadence.com
ASE Group – www.aseglobal.com
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
