System planner tool automatically generates 3D mechanical constraints

System planner tool automatically generates 3D mechanical constraints

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By eeNews Europe

System Planner includes new functions that allow design architects to study behaviour, signal quality, and 3D space constraints. Design Gateway includes improvements for hierarchy, rule checking, and an Intel Schematic Connectivity Format (ISCF) format for Intel design review. These enhancements, along with others in the CR-8000 2013 release, help design teams under tight deadlines reduce design iterations and deliver products to market faster. Zuken has streamlined the design flow for real-world engineering design, embedding multi-board SI analysis into System Planner.

This permits engineers to study behaviour and signal quality of system-level interconnections during the early design planning stage. It also facilitates "what-if" analysis to capture optimal topology and termination schemes earlier in the design process. Additionally, by importing accurate 3D enclosure and component models, engineers can create board outlines, see component profiles, and automatically generate mechanical constraints (such as height restrictions) for multi-board floor planning.

Enhanced design reuse supports drag-and-drop of logical and physical data from the reuse library directly in System Planner. These can be fed directly into the design flow with Design Gateway (logical design) and Design Force (physical design). Design Gateway’s Circuit Advisor, part of Zuken’s schematic engineering environment, includes new rule checks to support multi-board design for physical connector mismatches, I/O checks to ensure proper continuity between boards, and checks for duplicate references throughout the system. Simplified classification of nets and constraint entry allow you to easily define complex spacing requirements for high-speed interfaces such as PCI Express and DDR2/3/4.

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