Tachyum boosts universal processor design to 192 cores

Tachyum boosts universal processor design to 192 cores

Technology News |
By Nick Flaherty

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Slovakian data centre chip designer Tachyum has boosted the number of cores in its Prodigy universal processor to 192 following a move to a EDA provider.

Tachyum notably sued Cadence Design Systems over the IP it used in an earlier version with 128 of the patented cores based on  two 1024bit vector units and a 4096 matrix processor.

After the Prodigy design team had to replace IPs, it also had to replace RTL simulation and physical design tools. The new set of EDA tools from an unnamed provider allowed the designers to add more cores and more serial/deserialiser (SERDES) interfaces, going from 64 to 96 on each chip.

The company is now using IP from Alphawave and Rambus, whose physical IP has been sold to Cadence in an ironic move. It has been using the DesignWare Logic Library IP from Synopsys and DesignWare PVT Monitors and Sensors from Moortec throughout the design.

The next steps are to complete the substrate package and socket design to accommodate the additional SERDES lines but delivery of the first Prodigy high-performance processors remains on track by the end of the year says the company.

The additional cores saw the die size grew minimally, from 500mm2 to 600mm2 to accommodate improved physical capabilities. While Tachyum could add more of its very efficient cores and still fit into the 858mm2 reticle limit, these cores would be memory bandwidth limited, even with 16 DDR5 controllers running in excess of 7200MT/s

“We have achieved better results and timing with our new EDA PD tools. While we did not have any choice but to change EDA tools, our physical design (PD) team worked hard to redo physical design and optimizations with the new set of PD tools, as we approach volume-level production,” said Dr Radoslav Danilak, founder and CEO of Tachyum (above).

Other improvements realized during the physical design stage include increasing the L2/L3 cache from 128MB to 192MB and support for faster DDR5 7200 memory in addition to DDR5 6400. A larger package accommodates additional 32 serial links and as many as 32 DIMMs connected to a single Prodigy chip.

Tachyum describes Prodigy as a universal processor that can switch seamlessly and dynamically from normal CPU tasks to AI/ML workloads, so it delivers high AI/ML performance in both training and inference. The company points out that AI/ML is increasingly important in the banking industry, and used to identify fraud and cyberattacks before serious financial damage can be done.

The architecture is intended to reduce the operating and capital costs for data centre operators, particularly with shortages of Nvidia’s GPUs leading to higher costs, as the chip can be used for both high-performance and mainstream applications. The chip has up to four times the performance of leading x86 chips, three times that of the highest performing GPU for HPC and 6x for AI applications.

However this requires new a new software layer, which has been certified on an FPGA to run code for x86, ARM and RISC-V processors that are used in the data centre.


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