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Cadence and partners line up for pre-validated chiplets
Cadence and partners line up for pre-validated chiplets
Technology News |
Ever wondered what a chiplet is? Think of it as a small, specialised slice of silicon (a “die”) designed to…
Cadence tapes out UCIe IP at 64Gbps on TSMC N3P
Cadence tapes out UCIe IP at 64Gbps on TSMC N3P
News |
Cadence has taped out a third-generation Universal Chiplet Interconnect Express (UCIe) IP solution supporting data…
Partnership to develop next-generation AI chiplet
Partnership to develop next-generation AI chiplet
Business news |
CoAsia SEMI and Rebellions collaborate on the development and supply of an AI chiplet and server software, with verification by…
UCIe IP subsystem supports 36G die-to-die data rates
UCIe IP subsystem supports 36G die-to-die data rates
Technology News |
Alphawave Semi tapes out 36G UCIe IP on TSMC 2nm process to deliver 11.8 Tbps/mm bandwidth density critical for foundational…

First CMOS UCIe optical chiplet hits 8b Tbps bandwidth
First CMOS UCIe optical chiplet hits 8b Tbps bandwidth
Technology News |
The optical chiplet enables interoperability among different vendors and reduces latency and power consumption.
Fraunhofer picks Achronix eFPGAs for chiplet demonstrator
Fraunhofer picks Achronix eFPGAs for chiplet demonstrator
Business news |
Collaboration to create an eFPGA-enabled chiplet solution aimed at validating next-generation chip-to-chip interconnect technology.
Winbond to support chiplet interface standardisation
Winbond to support chiplet interface standardisation
Business news |
The UCIe Consortium open industry standard defines interconnect between chiplets within a package, enabling an open ecosystem.


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