The RISC-V Report – interviewing the key players (2017-2023)
Take time for the The RISC-V Summit in Barcelona and connect the dots of this Open Instruction Set Architecture
In 2017 we had the opportunity to interview Krste Asanovic about the Risc-V open ISA he developed with students from the Berkeley University. He visited the Barcelona Supercomputer Centre (BSC), one of the HPC Centres of Europe and a big supporter of the Risc-V Open ISA.
At that time it was difficult to say what the impact of RISC-V would be, it was too early, not many people had heard about it, but those up to speed predicted a bright future for this new standard that would allow to design silicon for processors without the usual ip restrictions.
One year later, in 2018, the BSC hosted on of the first RISC-V workshops. A small gathering, around 50 people, got together to discuss the latest developments and the latest products – RISC- V was picking up and drawing interest from the bigger players in the market; NXP was there, Andes Technology, Western Digital,… they all had plans. RISC-V had the potential to become a big player in the semiconductor world. Europe was (and is) interested in a more important role in the semiconductor world and it was unclear what role for example a company like ARM could play.
In this video you can catch up with history:
And now RISC-V is back in sunny Barcelona with a full blown summit. Around 500 people from all over the world are together to get informed, see new applications, discuss new research and dream of new plans. In 2027 the organisation expects that 16% of all semiconductor IPs will be RISC-V related, around 11,000 engineers all over the world are working with this Open instruction set architecture.
Find the interview with Calista Redmond at the RISC-V summit 2023 in Barcelona.
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