Tall metal can almost halve IC’s line resistance, says IMEC
Research institute IMEC has presented options for the reduction of metal line resistance at tight metal pitches in advanced ICs.
This is being proposed to help mitigate the otherwise inevitable rise in resistance/capacitance (RC) in future interconnects when using direct metal patterning.
IMEC is presenting experimental evidence in a paper at the 2022 IEEE International Interconnect Technology Conference (IITC 2022), on the use of high aspect ratio (AR=6) processing of ruthenium in a semi-damascene arrangement.
Damascening is the art of inlaying different metals into one another and has been used in back-end of line metal processing since the introduction of copper as a replacement for aluminium.
IMEC’s paper reports that the use of Ru in tall metal lines can result in about 40 percent resistance reduction without sacrificing area. Additional simulations confirm the benefits at circuit level in combination air-gap dielectrics. A complementary experimental study shows that the reliability of semi-damascene with air gaps is competitive when compared
to dual-damascene with low-k dielectrics.
IMEC provided the first experimental demonstration of a functional two-metal-level semi-damascene module at 18nm metal pitch, AR=3, with self-aligned vias at VLSI 2022. In the latest paper, IMEC proposes to extend this integration scheme to further reduce the line resistance of the ruthenium interconnects, while keeping the same footprint. This can be achieved by high-AR processing of the ruthenium lines using an advanced subtractive metal-etch process.
In a benchmark study, IMEC also demonstrated that the semi-damascene flow with airgaps is reliable with more than 10-years lifetime.
“With no less than 10 oral presentations at this year’s IITC, addressing the main challenges in interconnect scaling, imec has a proven path to push the interconnect roadmap for the coming ten years,” said Zsolt Tokei. “The papers cover advances in semi-damascene integration as a promising interconnect scheme for future logic nodes, memory
technologies and highlight progress in middle-of-line (MOL) metallization schemes, dielectrics, alternative metals exploration, and reliability.”
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