Tasking teams for Andes automotive RISC-V verification
Tasking in Germany has teamed up with Machineware to provide verification models and tools for the Andes RISC-V processor cores.
Tasking’s system-level verification and debugging tools now support the Andes RISC-V ISO 26262 certified Processor IPs and associated MachineWare Virtual Models. This collaboration equips SoC design teams with automotive-grade RISC-V IPs and the appropriate tools for early firmware and MCAL (Microcontroller Abstraction Layer) development.
Andes is set to launch an ASIL-B certified automotive RISC-V core, the D25F-SE, that supports the P-extension (SIMD/DSP) ISA draft for efficient manipulation of multiple data in a single instruction. This is expected later this year.
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The toolset released as part of the collaboration provides the capabilities for multi-core verification, debugging, performance tuning, timing, and coverage analysis. The toolset can be used with Andes RISC-V development boards and MachineWare high-performance virtual prototyping solutions. The Tasking iSYSTEM debug adapters will also be available to support Andes RISC-V processors to enable the connection with the toolset.
MachineWare’s virtual prototypes support the simulation of complex hardware/software systems for software analysis, verification and development as well as architecture exploration. With SIM-V MachineWare offers a high-speed RISC-V simulator that can be integrated in a full-system simulation, or Virtual Platform (VP) to simulate entire SoCs or ECUs. Besides pre-silicon availability, VPs offer advantages over physical prototypes, as they enable for deep, non-intrusive introspection and are scalable either on-premise or in the cloud.
The combination of products from the three companies enables users to switch seamlessly between virtual and physical SoCs, applying the same tools and automation scripts without any changes to the users’ process. This allows software developers to start the development process before silicon is available and identify and fix potential bugs and security issues at an early stage, shortening time-to-market.
Gerard Vink, responsible for RISC-V at TASKING, is excited about the collaboration of the three companies: “This partnership offers an integrated solution needed to drive the adoption of RISC-V based SoCs in the automotive domain. The certified IPs and tools reduce the efforts of all parties in the supply chain to comply with functional safety and cybersecurity requirements, enabling them to focus on innovation and product differentiation.”
“Andes’ ISO 26262 certified RISC-V IP offers solid, unprecedented flexibility and efficiency in silicon development”, said Samuel Chiang, Deputy Marketing Director of Andes, “Together with TASKING and MachineWare, we empower customers in the automotive industry to accelerate their development efforts, ensuring the successful achievement of functional safety and cybersecurity protection.”
Our ultra-fast SIM-V functional RISC-V simulator empowers engineers to simulate complex hardware/software systems long before physical prototypes are even available. This speeds up the development process and reduces expensive bugs”, said Lukas Jünger, co-founder of MachineWare. “We are proud to collaborate with TASKING and Andes to offer our customers the tools they need for developing SoCs for the automotive industry.”
www.tasking.com, www.andestech.com and www.machineware.de
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