Over the last year and a half, the major NAND flash makers have started selling their 1X nm class of planar flash memory. According to our sourcing of the devices on the open market, summarized in Table 1, Micron was first with product appearing in February of 2014, followed by SK-Hynix in October. Nearly 6 months later, products sporting Samsung 16 nm or Toshiba 15 nm NAND flash showed up in our laboratories.
There has been much discussion in the literature on the end of lithographic scaling of planar NAND flash, and its replacement with vertically stacked flash such as Samsung’s 3D V-NAND or Toshiba’s BiCS. There is a consensus that planar NAND will end near the 10 nm node, that is, one or two generations into the future from the 15/16 nm NAND flash that we at TechInsights are now completing analysis on. We thought it timely to look at some process features that we see in these 15/16 nm flash memories.
Table 1: TechInsights Receipt of 1X nm Class NAND Flash (Source: TechInsights Receipt of 1X nm Class NAND Flash, TechInsights)
We have been buying NAND flash memory for a number of years for our technical analysis reports and Figure 1 shows the process nodes versus year that we acquired them for Micron and SK-Hynix. These two manufacturers were typically the first to market with a process node. A semi-log plot is used to show the roughly 23%/year process shrink (solid black line) that we see for the Micron and Hynix devices.
The rate of process shrinks has slowed dramatically for the 25 nm and smaller product and this likely reflects the difficulties in implementing double patterning lithography and reducing electrical interference between adjacent cells.
Two approaches can be used for double patterning. Litho-etch-litho-etch (LELE) double patterning (DP) that is typically used for logic processes, or self-aligned double patterning (SADP) using sidewall spacers that is used by the memory makers. This has worked for NAND flash devices down to the present 16 nm node but may not make it to the 10 nm class of devices.
But scaling down to planar 10 nm NAND flash is still seen as a significant challenge and this has spurred efforts to develop 3D vertical NAND flash memory. For completeness, we include Samsung’s 3D V-NAND in Figure 1 as it is the first commercially available part. Toshiba, Hynix and Micron will likely introduce their 3D NAND product in the near future.
Figure 1: Observed Process Nodes for Micron and Hynix NAND Flash vs. Year (Source: Figure 1: Observed Process Nodes for Micron and Hynix NAND Flash vs. Year, TechInsights)
Double patterning patterning has become mandatory for making the 16 nm node NAND flash and the memory makers use a self-aligned double patterning (SADP) for the active, control gate, floating gate and bitline patterning. The SADP process sequence from making the initial pattern, through the sidewall spacer etch back to the double pattern transfer is shown schematically in Figure 2.
The double patterning process can often result in an asymmetry in the spaces between the final sidewall spacer structures that is seen as an AB patterning. And this is readily seen in the STI patterning of the Micron 16 nm NAND flash shown in Figure 3.
A tungsten metal word line is seen running left to right overtop a series of planar floating gate structures that are aligned to the underlying silicon channels. The floating gates and silicon channels have been patterned and etched together using a SADP process. The bottoms of the shallow trench isolation (STI) between adjacent silicon channels exhibit the characteristic AB pattern in their etch depths, indicating the use of a self-aligned double patterning process.
SK-Hynix used a quad spacer patterning for their M1X nm floating gate NAND presented at IEDM 2013 and this is likely being used for their 16 nm NAND flash shown in Figure 4. The AB pattern at the bottom of the trenches is largely absent being replaced with a more random patterning. We see similar random patterning with the Samsung 16 nm and Toshiba 15 nm NAND flash memories, perhaps indicating that they too are using a quad spacer patterning process.
The next design problem is to maintain a high capacitive coupling between the control gate and floating gate, while minimizing the capacitive coupling between adjacent cells. Traditionally, the control gate (CG) is wrapped around three sides of the floating gate (FG) as shown in Figure 5.
The interpoly dielectric (IPD) provides the capacitive coupling between the CG and FG and it needs to have excellent blocking characteristics to current and a high dielectric constant k. Hynix’s oxide/nitride/oxide (ONO) layers can be seen in Figure 5.
The IPD is fairly thick and this reduces the gap for the control gate fill between the adjacent floating gates. Hynix has thinned down the sides of the floating gates to provide more room for the control gate. But the opportunities for continued shrinking of the NAND cell pitch in this direction is limited if one wants to maintain the control gate over the three sides of the floating gate.
We note that Hynix has added air gaps between the silicon channels (active air gap) to reduce their capacitive coupling.
Micron has eschewed the wrap-around control gate in favour of a planar control/floating gate structure for their 16 nm NAND flash. This is not their first time for using a planar gate structure, as we also observed it in Micron’s 20 nm NAND flash memory.
The gate structure is shown in Figure 6. Micron has retained the polysilicon floating gate but it is now quite thin. This allows the HfO2/oxide/HFO2 interpoly dielectric layers to lie nearly flat overtop the floating gate, and the very high dielectric constant of the HfO oxide layers yields sufficient capacitive coupling between the control and floating gates to eliminate the need for the gate wrap around structures that are used by Hynix, Samsung and Toshiba.
Shrinking of the word line and bitline pitches has exacerbated the capacitive coupling between adjacent cells. This is a problem as the programmed state of the one cell can be capacitively coupled to the adjacent cell.
This can result in disturbed cell threshold voltages (VT) and misread bits. Air gaps between adjacent word lines have been used for a number of years to reduce their capacitive coupling and Figure 7 shows an example of this used by Toshiba for their 1st generation 15 nm NAND flash.
The floating gate air gaps used by the Samsung 16 nm NAND are shown in Figure 8. These air gaps are much less uniform that Toshiba’s. This would suggest that the Samsung cells will show a greater variability in cell-to-cell cross-talk and this might show up as increased overhead for the cell write and erase times.
The opportunities for continued lithographic shrinking of planar NAND flash seem limited as immersion lithography with quadruple patterning may only get to the low 1X nm node, and air gaps are already being extensively used to suppress cell-to-cell interferences.
The gate wrap around structures used by Samsung, Hynix and Toshiba may scale to about 10 nm and Micron’s planar floating gate might get them to sub-10 nm geometries. But in the end, NAND flash will go vertical. And here, Samsung was first off the mark with the release of their 3D V-NAND flash in the summer of 2014. Click here to learn more about TechInsights analysis of the Samsung 3D V-NAND.
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