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Technical conference supports chiplet paradigm

Technical conference supports chiplet paradigm

Technology News |
By Peter Clarke



One of the highlights of the upcoming IEEE Electronic Components and Technology Conference (ECTC) will be a complete computer the size of a grain of salt.

At the conference – which takes place in Denver, Colorado, May 28 to 31 – IBM researchers will describe a computer that comprises a 32-bit processor, memory, analog I/O, built-in temperature and chemical sensors, an energy-harvesting power source, and operating system software.

IBM will provide details of a high-throughput chiplet packaging process for use making sensor data acquisition and secure communications components for military, commercial and consumer applications. The process makes it possible to build a complete computer system on a substrate that is less than 1 square millimeter. The process incorporates wafer-to-wafer (W2W) transfer, with integrated Si and/or III-V optical photovoltaic/photodiode cells fabricated on Si carriers.

Although the conference is the 74th of that title, it comes at a time when there is increased interest in multi-die packaging and so-called ‘chiplet’ manufacturing. These techniques support memory assemblies; sensors with local signal conditioning and logic; photonics and increasingly complex logic for AI and quantum computing applications.

In a keynote talk, Columbia University Professor Keren Bergman will discuss the opportunities and challenges of co-packaging to make possible higher-performance, more energy-efficient data centers for AI computing. 

Photonics

On that theme researchers from Broadcom and Siliconware Precision Industries are set to describe the world’s first 51.2Tbps Ethernet switch system with co-packaged optics for data center connectivity. It quadruples the bandwidth of widely-deployed 12.8 Tbps networking solutions, and leads to a significant reduction in overall power consumption per bit transmitted. It makes use of silicon photonic (SiPh) chiplets co-packaged with silicon switch die on the same substrate, with short interconnects. The researchers built a prototype that co-packaged eight optical engines with switch die.

There are several papers that discuss so-called backside power delivery, or how you can get power to all areas of 3D device “skyscrapers.”  Samsung will discuss three different ways to do it.

The range of topics to be covered at ECTC 2024 includes heterogeneous integration, photonics, components, materials, assembly, reliability, modelling, interconnect design and technology, 2.5D/3D integration technologies, direct/hybrid bonding, device/system packaging, wafer-level packaging, optoelectronics and more.

“Transistor scaling has become much more challenging and costly, and so advanced packaging and component technologies have become critical enablers of progress in high-performance computing, advanced smart phones, the Internet of Things (IoT), 5G/6G communications, quantum computing, and more,” said

“This year brings the largest edition of ECTC to date, with papers covering a broad range of related topics, and with a major focus on highly promising technologies that are enabling heterogeneous integration and photonics,” said Professor Michael Mayer, 74th ECTC program chair, in a statement.

Related links and articles:

www.ectc.net

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