Technical considerations and protection mechanism for ESD events in a mixed signal SoC – part 2

Technology News | August 1, 2012

By eeNews Europe

Figure9: A Typical SOC

In most of the cases, all these analog IP’s have separate isolated power supplies at chip level due to reasons like noise and different operating voltage level. Digital part in SoCs is also divided in multiple power domains to save the overall power in low-power modes. The signals from outside world interact directly with the analog IP interfaces. The designer has to keep an account of the ESD protection available for each external interface, i.e., I/O pins and power pins. Due to different power supplies and analog to digital interface communication or vice versa, there are several signals crossing from one power domain to another as a result the analog IP’s required to have an in build ESD protection.

Before going in detail for ESD protection mechanism, few combinations for ESD on SoC need to understand as mentioned below:

The signal from external I/O goes directly to an analog IP working on isolated supply.
The signal from analog IP which works at isolated supply goes to digital interface in SoC or vice versa.
The signal from external I/O goes to digital logic in SoC.

Best practices for analog IP signal connections to external I/O and digital interfaces:

Below are the different points that need to be taken care for ESD protection while connecting to an analog IP pin to external I/O or digital interface.

Add small diodes called spot diodes in analog IP when the gate of a device in analog IP is connected to external I/O interface. These diodes will be connected from the signal to power/ground supply at which the receiving analog IP is working.
When a signal from external I/O is connected to gate of analog IP, use the resistive path from the external I/O “pad” pin for connection. It is always recommended to add small diodes after the resistor from the signal on I/O pad to the I/O pad power and ground rails. You may skip the resistive path if there are special requirements on some signals from delay perspective.
There should be ESD protection placed on the each port of analog IP which receives the signal from the digital SOG and similarly the port of digital IP which receives signal from the analog IP should have ESD protection.
There should be back to back diodes placed between the isolated ground of analog IP and the substrate ground.
Any unbonded pin should be left unconnected on package, rather tie the unbonded pin to ground.

Figure10: Analog IP connected to external I/O ESD protection with spot diodes

In padring design, there may be different banks depending on various interfaces involved in SOC. By bank, we mean a segment in padring which has IO cells working on same voltage. Generally there are different banks (as shown in figure9) for critical analog IP interfaces like ADC, USB video ADC etc as they have their own supply and the GPIO bank supply might induce noise on the signals. The number of banks in a padring also depends on the voltage level of the interfaces involved in a SOC. Interfaces working at different voltages need to be placed in different banks in a padring. Each IO bank in padring has its own power and ground supplies. These power and ground rails must be continuous in an IO bank. The ESD current is carried by these power and ground rails. There are also core power and ground rails in the IO cells which interfere with the core logic sitting inside the SOC and there are core power and ground pads having the protection clamps sitting in padring. The designer has to make sure that the substrate ground rail is continuous throughout the padring for proper ESD protection.

Role of Rail Resistance in ESD Protection in SOC design:

The term rail resistance signifies the power and ground rail resistance when an ESD event occurs, the ESD current flows through the primary ESD protection diodes connected to the power and ground rails. The current then flows from the power rail through the ESD clamp to the ground rail, which then goes out the SOC through package pin. So current is finally sunk to a bonded ground pin. The rail resistance plays an important part in the ESD protection design. Current always flows through the least resistance path. So it is important that the ground pad which acts as a sink for the ESD current is placed nearby the signal pads. In distributed clamp strategy, there are small clamps in each IO pad (including power and ground) and trigger circuit is generally in the power pads. So the padring designer should consider placing the power and ground pads uniformly and frequently enough to route the ESD current to the ground pad. The power and ground pad placement is also driven by the SSN limit of the interface.

Let’s take some classic cases where the designer needs to ensure the rail resistance is least.

CASE I: While designing the padring for SoC, the designer needs to ensure the clamp width should be sufficient enough to support the ESD current path for every interface. Now there are two options available, either add sufficient clamp in the padring at the particular supply or one can place clamp cells inside the core area, if there is not enough space available in padring. For the first option, if the designer has enough space in padring, one can place the extra power pads for the particular supply having sufficient clamp width but there may be a case that due to package and bonding limitations, the designer is not able to bond these pads and they are placed at some distance from the bonded supply pad. So now the effective rail resistance for the power rail increases and a possibility that current may flow through the circuit arises, which seems as low resistance path. Now even if the designer has added enough clamp width in padring design, the ESD current will damage the circuit. So in such cases, the designer has to ensure that these supply pads having clamp cells are connected with least possible resistance, preferably of the order of 0.25ohms. This will make sure current flows through the clamp cells to the ground rail, which is desired ESD current path. For the second option, if the designer does not have space in the padring, then one can opt to put the clamp in the core region of SOC close to the supply pad and connect the clamp to supply and ground pads which least possible resistance, again preferably of the order of 0.25ohms. Below figures11 and figure 12 explains the implementation of the first option and second option respectively.

Figure11: Implementation showing unbonded pad with extra clamp cell placed in padring and intended ESD path

Figure12: Implementation with extra clamp cell in Core area and intended ESD pat

2. CASE II: This case is be related to the isolated supply and ground pad requirements to any analog IP. In most of the cases, there is a requirement to put an isolated supply and ground pads for analog IP on die. These are not shorted on die with any other supply but may be shorted to other supplies at package or board level. There are requirements of putting some special supply pads for a particular power/ground pin of any analog IP and the designer may not have dedicated pins on package to bond these pads. So the designer has to share these supplies with same voltage level supply available at die. Usually the special isolated power and ground pairs are required to be put in pair as they together form an ESD protection circuit and the pad type used are feed-through pads or dedicated power/ground pads. But since the pads are unbonded, they are of no use for ESD protection.

Let’s take the case of unbonded ground pad here. Now, the designer has to provide a sink path for ESD current from this unbounded ground pad to a bonded substrate ground pad. There will be rail resistance (RRAIL) of the substrate ground rail from the unbounded isolated ground pad to bonded substrate ground pad. This rail resistance may be high enough that ESD current flows through the circuit which needs ESD protection and damages the circuit. So the designer has to create a low resistance path from the isolated ground to the bonded substrate ground pad. Again the resistance desired for this path is of the order of 0.25 ohms (shown in figure 13 in black). This will save one extra bonded pad required of the dedicated supply pad for ESD protection.

Figure13: Implementation for a special supply pads for an IP (no package pin available for this ground)

Now there will be a voltage build up across this low resistance path, RESD. So the designer has to understand that the ESD protection is with respect to the isolated supply and ground, not the bonded substrate ground. This voltage build up can damage the analog IP circuit if the designer does not follow the proper implementation, which is demonstrated in below figure14.

Figure14: Implementation to be followed for ESD resistance paths.

3. Case III: This is the case for ESD protection where the clamp for a particular supply is sitting inside an analog IP. As the analog IP is placed inside SOC, and the supply is connected to the power pads in padring. The top level routing at SoC from the pad to the supply port of analog IP may be resistance enough that in case of ESD event, there are less resistance paths available through circuit, resulting in ESD current to flow through the circuit and hence damaging the circuit. In such cases, it is advised to add an extra clamp at top level and route it with least resistance possible preferable with 0.25 ohm. This will make sure that the ESD current flows through the clamp and sunk to the substrate ground.

ESD failures

An ESD event may cause permanent damage to a chip or there may be partial damage to the chip such that the chip is functional but suffers degradation and in longer run the chip fails. The assembly yield is also affected by ESD event.

The NMOS in output buffer stage is more prone to damage as compared to the PMOS. Due to higher mobility of electrons as compared to holes, the parasitic bipolar action in NMOS is more efficient. As a result, NMOS can be easily turned on in case of ESD event as compared to PMOS. There are various techniques to detect ESD failures like Liquid crystal Analysis, Light Emission Microscopy etc. To detect the ESD failure, change in leakage current at stressed pin is observed through one of the detection techniques as mentioned above. Following are the common types of ESD failure:

1. Transistor Gate oxide Breakdown: Gate oxide breakdown (shown in figure 15) is referred as the destruction of the oxide layer. The oxide layer used in semiconductors is generally silicon dioxide. There is a threshold voltage level which the oxide layer can sustain. If, during an ESD event, the voltage build up across the oxide layer is greater than this threshold voltage, the oxide breakdown or punch through can happen. As device geometries are shrinking with technology and gate oxide thickness is decreasing, this is one of the prominent ESD failures that can happen. The leakage current change is of the order of 1mA.

Figure15: Transistor Gate Oxide Breakdown

2. Transistor Junction Damage: The p-n junction in transistor can be damaged by the ESD event and it may cause short or open circuit. The junction damage can be seen at the diffusion edge in NMOS transistors used in output buffer stage and input/output protection. The leakage current is of the order of uA in junction damage.

Figure16: Drain Junction Edge Damage

3. Transistor Filamentation Damage: The high currents in an interconnection can rise the temperature to the melting point. Due to current filamentation, large melt regions are observed between the n+ diffusion regions in NMOS transistors. Silicided processes generally show these kinds of failures. Change in leakage current can be of the order of 1uA to 100uA. 2kV or more ESD stress level show these kinds of failures, but if the protection or output buffer is weak, then the damage can also occur at lower ESD stress levels.

Figure17: Transistor Filamentation Damage.

So to summarize, change in leakage current and associated failure modes can be listed as below.

If change in leakage current after ESD stress = 0, then there is no damage occurred to device due to ESD event.

If change in leakage current of the order of 1- 100 pA, then there can be drain-to-source filamentation damage.

If change in leakage is in range of 50 to 100 pA, there can be contact spiking.

If change in leakage current > 1 mA, silicon melting or gate oxide breakdown has occurred.

Conclusion:

ESD is a primary concern as we are moving to deep sub micron technologies. These deep sub micron technologies provide the benefits of higher speed, more gate density, lower power dissipation and low manufacturing cost per die to the designer. But there are other factors like thinner gate oxide and multiple power domain requirements. These factors increase the risk of chip damage due to ESD event. Due to multiple analog IP interfaces and multiple power domains in the design, there are multiple signals going from one domain to another. The designer has to consider ESD protection for all the cross domain signals and chip interfaces with the outer world.

The paper covers the ESD basics protection mechanisms including their characteristics of a good ESD protection methodology and trigger circuit design followed the by actual protection and use cases for a mixed signal SOC. The aim of the paper is to familiarize and sensitize the designers towards various factors and protection techniques for ESD protection in mixed signal SOC. The various types of ESD failure types are also discussed.

References:

[1] Michael Stockinger, James W. Miller, Michael G. Khazhinsky, Cynthia A. Torres, James C. Weldon,Bryan D. Preble, Martin J.Bayer, Matthew Akers, and Vishnu G. Kamat, “Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies”

[2] Ajith Amerasekera, Charvaka Duvvury, “ESD in Silicon Integrated Circuits”

[3] https://www.eetimes.com/design/audio-design/4013337/Engineer-s-guide-to-HDMI-ESD-protection-Part-1

[4] https://www.ce-mag.com/archive/03/ARG/dunnihoo.html

[5] https://www.electronicspub.com/articles/articles.print.php?id=26

[6] https://www.sjsu.edu/faculty/selvaduray/page/engr242/Lecture%204.pdf

[7] https://en.wikipedia.org/wiki/File:GGNMOS_CUTAWAY.png

Authors:

Gurinder Singh Baghria: Working as a Design Engineer at Freescale Semiconductor, India Pvt Ltd having 2 years of experience and mainly responsible for SoC Physical design activities. Floorplanning, power planning/estimation and IR drop analysis (Static/Dynamic) are the main expertise and focus areas. Received B.Tech degree in Electronics instrumentation and control from the Thapar University.

Naveen Kumar: Working as a Sr. Design Engineer at Freescale Semiconductor, India Pvt Ltd having 4 years of experience in SoC Physical design activities. Padring integration, Floorplanning, Power Planning/Estimation, IR drop analysis (Static/Dynamic), and physical verification are the main expertise and focus areas. Received B.Tech degree in ECE from NIT, Kurukshetra.

Rishi Bhooshan: Working as SMTS (Senior Member of Technical Staff) at Freescale Semiconductors, India Pvt Ltd having experience in the area of Physical design, chip design tools, flows and methodology including design methodology such as low power design, power integrity and signal integrity, ESD/EMC and reliability.

Sachin Kalra: Working at Freescale Semiconductors, India as Senior Design Engineer and 6 years of experience in Physical Design, Analog Layout Design and Standard Cell Library Design. Received his M.Tech in Electronics and Communication form Thapar University.