Technical considerations and protection mechanism for ESD events in a mixed signal SoC

Technology News | July 25, 2012

By eeNews Europe

REQUIREMENTS OF ESD PROTECTION MECHANISM AT SOC

The sole aim of ESD protection strategy is to divert the ESD current spike away from sensitive circuitry and protect the system from permanent damage.

Figure 1: System Level Network Presentation

An ESD protection mechanism must fulfill the below requirements:

It must provide dual polarity protection, i.e., should provide ESD protection in case of both positive and negative spikes.
The ESD protection device must be able to handle high current transients.
The ESD protection path must have very low resistance in case of ESD currents. Typical resistance value is 1 ohm.
The ESD protection device clamps the voltage of sensitive circuits below safe functional voltage level.

The typical ESD protection methods used in SOCs are:

· Distributed rail based clamp network; and

· Snapback clamp protection devices.

Snapback Protection Method: The conventional snapback clamp protection method depends on the theory of avalanching junctions to trigger parasitic LNPN (lateral NPN) or Silicon Controlled Resistor (SCR). Most popular protection devices in snapback method are MOSFET and SCR. Under ESD conditions, these devices operate in breakdown region. The most important features of snapback based protection are as follows:

It can be made robust by optimization.

Being generally immune to false triggering, it can be used for fail safe applications.

On the other hand,

It is very much process dependent and difficult to simulate.

A ballast resistance is required to protect the NMOS output buffer.

The protection clamp may occupy large layout area and may add significant capacitance to IO pad.

The typical snapback I-V characteristics of protection device (Grounded gate NMOS) are shown in figure 2(b). With the increase in drain voltage, many electron-hole pairs are generated by impact ionization and the drain substrate junction of parasitic LNPN shown in figure 2(a) becomes more reverse biased and eventually goes into avalanche breakdown. Electrons that occur due to impact ionization flow to the drain and holes flow to the substrate so a potential start rises across the base of transistor and when this potential reaches 0.7V, the transistor gets forward biased and turns on. At this point, the drain voltage is marked as Vt1 and is called first breakdown voltage. The drain voltage is reduced to a level marked as VSB, (holding voltage) and from this point on, increase in the drain voltage increases the current until finally the device goes through thermal breakdown. This second breakdown voltage is marked as Vt2.

Figure 2. For full resolution click here.

Figure 3: Snapback ESD protection scheme

RAIL BASED NON SNAPBACK Protection: This protection mechanism uses clamp circuitry connected between the power and ground rails as shown in figure 4. The clamp used is usually a large NMOS device which is triggered by a RC network which senses the voltage spike between the power and ground rails. The clamp is capable of carrying high currents without going into avalanche breakdown region. It is at the sole discretion of the designer whether to go for a large clamp cell in one I/O cell or to go for distributed clamps in various I/O cells placed in the design decided based on factors like layout area, etc. In distributed rail clamp methodology, the large clamp is broken down into small clamp cells placed in each I/O cell. It provides the best optimized layout area and uniform ESD protection. Following are the advantages of this protection methodology:

As there is no breakdown involved, the circuit behavior can be easily simulated.

Process portability and scalability is there.

Reduced capacitance is added to I/O cell.

Figure 4: Rail based clamp Cell Protection

ESD Pulse and ESD trigger circuits:

Let us now briefly explore the behavior of ESD pulse and how the ESD trigger circuit functions in case of an ESD event. A typical ESD pulse is shown in below figure 5. The rise time of ESD waveform is generally 0.7ns to 1ns and the decay time to 50% of maximum current value is about 60ns.

Figure 5: A typical ESD Pulse

The ESD trigger circuit is required to sense the ESD event in the rail based ESD protection mechanism and turn on the ESD clamp till the end of ESD event which is of duration in range of 500ns to 1us. The ESD trigger circuit senses the fast rising voltage signal. This mechanism may also lead to false triggering during the normal power up sequence when the rise time of voltage is detected as an ESD event. Therefore need arises to have ESD detection range equal to the maximum rise time of ESD event so as to maximize the voltage rise time during normal power up.

Figure 6: Conventional ESD Trigger Circuit

Figure 6 shows a conventional ESD trigger circuit which is designed with the RC filter and having three CMOS inverters stages. The RC filter and first inverter known as detector stage is used to detect the rise time of the pulse. Second and third inverter forms a predriver and the stage is known as pre-driver stage which drives the gate of the ESD clamp cell. When an ESD pulse arrives, the RC stage delays the voltage rise at input node of first inverter and the output drives the clamp circuitry. The important point to note here is this circuit uses same time constant for detection of ESD event and ESD clamp turn on control. Since the ESD clamp must be kept on for the entire ESD duration of 500us to 1ns, the RC time constant must be high (e.g. of the order of 800ns). This kind of scenario increases the risk of false triggering during normal power up sequence.

To overcome such issues, there is another trigger circuit shown in figure 7 is used which has separate time constant for the ESD event detection and on time control of the ESD clamp. The ESD detection stage time constant is designed as per the rise time of ESD event and the time constant for the predriver stage driving the ESD clamp cell is set as per the total time of ESD event, i.e., ~600ns. In this kind of design, there is a separate on time control circuit for ESD clamp. The rise time detector circuit provides a short pulse to the MOS M1 (shown in figure), which then turns on the ESD clamp. This MOS M1 will turn off once the voltage pulse provided by the detector is over. Now the capacitor, C1, will discharge slowly through the resistor, R1 and keeps the ESD clamp on for the duration of the ESD event. This design eliminates the change of false triggering during normal power up and requires small R & C values.

Figure 7: ESD Trigger Circuit with separate Rise time detection and on time control

The clamp MOS gate is driven by the ESD trigger signal. So the designer has to take care of the capacitive load due to MOS clamp, which is to be driven by the trigger circuit. So placement of trigger circuit is also a key element in ESD protection design.

Quality measures of ESD protection network:

It is required for a quality ESD network to provide a discharge path for all pin combinations and also limit the voltage across the sensitive circuits, particularly output buffer stage. The capability of an ESD network can be measured in four categories, robustness, effectiveness, speed and transparency. Good ESD protection must function well in all these four areas. Let’s take a quick look at these measures.

1. Robustness: It is the ability of the ESD clamp cell to handle the high ESD current by itself. It is defined as the ESD level at which the clamp, taken on its own, fails. The designer can measure the characteristics of the clamp cell using the transmission line model or HBM testing to quantify the failure level of the clamp cell. The robustness is generally taken as directly proportional to width of the clamp cell. The designer must keep some margins for process variations while deciding width of the clamp cell.

2. Effectiveness: It is described as the ability of ESD clamp network to limit the voltage to a safe operating level so that the circuits connected in parallel that need to be protected by this clamp network do not fail. The case should be that the clamp cell itself is constrained to 4kV of HBM but the IO circuitry, like output driver or some other parasitic path, activates at 2kV HBM. Thus, the clamp cell is effective at 2kV HBM only for this IO network. The designer has a choice to mark a 2kV HBM protection for this network or increase the turn on voltage of the circuit in parallel or decrease the sustained voltage level of the protection clamp network to increase the protection level of network.

Figure 8 shows the I-V characteristics of protection clamp and circuit in parallel path under ESD conditions. The desired protection level of the sensitive circuits (parallel path) is IESD. In Figure 8 (a), the protection clamp device is able to withstand the IESD level. The protection clamp triggers and conduct at voltage level less than the failure voltage level of devices connected in parallel path. The voltage level is maintained much below than the failure voltage for parallel circuit even when the current is of the order of IESD. So this clamp cell forms an effective ESD protection network for the parallel network path. In the characteristics shown in figure 8 (b) and figure 8 (c), the sensitive circuit in parallel path, that needs to be protected by the clamp cell, conducts earlier than clamp cell but eventually due to the resistive nature of the parallel network, the clamp cell triggers at voltage below the failure voltage level of parallel circuit. So now the ESD current flows through the protection clamp device.

Hence this is also effective and robust ESD protection network. Figure (d) shows the characteristics which depicts that the circuit in parallel path triggers at lower voltage level than clamp cell and the current flows through the circuit instead of clamp cell. In this scenario, the devices in parallel path are damaged due to ESD current. In scenario shown in figure 8(e), the ESD clamp network triggers at lower voltage but the clamp circuit provides much more resistive path than the parallel circuit and therefore the ESD current flows through the devices in the parallel path and damages them. Similarly in the figure (f), due to resistive nature of ESD clamp path, the current flows through the circuits and devices fail ESD compliance. So standalone clamp cell shown, in figure 8(d) to figure 8(f), is able to handle ESD current level of IESD and hence robust but the clamp network is not able to protect the parallel sensitive circuit making it an ineffective protection network.

Figure 8: I-V characteristics of ESD clamp and parallel circuit showing effective (figure (a) to(c)) and ineffective (figure (d) to (f)) protection.

3. Speed: The ESD network must trigger and conduct within enough time to limit the voltage level for the sensitive circuit. If the protection network triggers slowly and voltage across the sensitive circuit builds above tolerable margins, then it can damage the circuit and the protection scheme fails so speed is an important factor in ESD protection networks, especially in CDM events.

4. Transparency: The ESD protection network should not interfere with the normal functioning of chip and IO cells. The various factors that can be counted to affect the IO parameters and specifications are as below.

a) Capacitance: The clamp network poses an extra capacitance overhead to the IO network. The IO cells have well defined specifications of performance under different load conditions. These specifications should not be violated with the load limits of IO cells.

b) Power sequencing: The normal power up sequence should be compatible with ESD clamp. The ramp rate of normal power up should not be considered as ESD event.

c) Leakage Power: The clamp circuitry should not draw excessive currents to violate the design specifications.

Transparency is an important factor for high frequency interfaces.

To summarize, before applying ESD protection, a designer needs to understand the boundary conditions of the IO network to be protected. The variables are listed below.

Type of Node/Pin – Internal/External: If the node is internal to the chip, then it may not need extra clamp protection on board.

ESD Protection Level: It is the clamp voltage level that the chip can tolerate.

Tolerable line impedance to signal line: It is the amount of extra line impedance that signal lines can tolerate without distorting the quality.

Part two of this series will deal with ESD Protection in Mixed Signal SOCs

About the authors:

Gurinder Singh Baghria: Working as a Design Engineer at Freescale Semiconductor, India Pvt Ltd having 2 years of experience and mainly responsible for SoC Physical design activities. Floorplanning, power planning/estimation and IR drop analysis (Static/Dynamic) are the main expertise and focus areas. Received B.Tech degree in Electronics instrumentation and control from the Thapar University.

Naveen Kumar: Working as a Sr. Design Engineer at Freescale Semiconductor, India Pvt Ltd having 4 years of experience in SoC Physical design activities. Padring integration, Floorplanning, Power Planning/Estimation, IR drop analysis (Static/Dynamic), and physical verification are the main expertise and focus areas. Received B.Tech degree in ECE from NIT, Kurukshetra.

Rishi Bhooshan: Working as SMTS (Senior Member of Technical Staff) at Freescale Semiconductors, India Pvt Ltd having experience in the area of Physical design, chip design tools, flows and methodology including design methodology such as low power design, power integrity and signal integrity, ESD/EMC and reliability.

Sachin Kalra: Working at Freescale Semiconductors, India as Senior Design Engineer and 6 years of experience in Physical Design, Analog Layout Design and Standard Cell Library Design. Received his M.Tech in Electronics and Communication form Thapar University.