Technology talk at IMEC Forum

Technology talk at IMEC Forum

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By Peter Clarke

IMEC’s view of the system domain divides into three principal areas; IoT and deeply embedded; mobile processing and high performance such as servers. This is how they map against power and performance. Also shown are the manufacturing processes in use in the three zones and where they are moving towards. However, those days of happy scaling have been over for a while, Steegan said.

Next: High performance scaling

Steegan then shows Moore’s Law to be more or less alive with FinFET progress seen as possible until 5nm. At 20nm double patterning kept the show moving forward but at a cost. 14nm and 10nm need triple patterning and raised costs higher but the introduction of EUV at 7nm is expected to pull cost back down. Further development is enabled partly by design and technology co-optimization. In other words engineers must change how they design to allow process shrinks to continue. The trade off is standard cell track height reduction and the reduction of the number of fins and flexibility available for drive from 7.5 to possibly just two.

Next: FinFETs down to 5nm, then nanowires?

Power performance scaling with FinFETs down to 3nm although at this point nanowire transistors should show superior area-performance trade off, Steegan said. “The 3nm nanowire performance is on par with FinFET and has better electrostatic control,” Steegan said in a side meeting with the press about the technical presentation. Lateral nanowires can be, in effect, a pinched off fin but with potentially multiple wires in the physical fin. IMEC has made fins containing up to eight lateral nanowires, Steegan said. They can be partially defined by specialized material such as germanium in the channel.


Extreme ultraviolet lithography is almost there with great progress made on source brightness and therefore throughput as this slide shows. However, resist and resulting line-edge roughness are requiring additional post exposure processes and masks need to be made more robust.

Next: CNT in the pellicle

IMEC is working on pellicles made of a carbon nanotube (CNT) matrix film. Pellicles are used to protect the mask but with EUV being essentially soft x-rays there is a need to minimize the amount of material in the mask to prevent absorption of energy. Carbon and graphene can be damaged by EUV due to the release of electrons but IMEC reckon that when coated with a metal film the CNT provides strength and protection along with 97% transmissivity, Steegan showed.

Next: Scaling boosters

Cell library scaling in the y direction can help with FinFET area scaling down to 3nm or 2nm but with a loss of fins enabled by other techniques, Steegan said and referenced the use of self-aligned gate contacts, super vias, buried power rails and vertically oriented complementary FinFETS. Vertically oriented complementary tunnel-FETs may be a possibility thereafter.

Next: System-technology co-optimization

Steegan then turned to what technology would get the semiconductor industry below the 3nm node and offered that it could be the addition of system-technology co-optimization which may come in the form of hybridized scaling for different parts of the SoC such as logic, memory, I/O, analog.

Next: Hybridized scaling?

There are several ways such hybridized scaling could be imagined as working, Steegan said. One is the ability within a monolithically integrated system on a single substrate to apply different process technologis, such as nanowire fins for logic, MRAM for embedded cache memory and superscaled FinFETs for the highest performance CPU cores. The question is whether such a hybridized process can be performed cost-effectively in a single pass.

There are alternatives such as two pass production with face-to-face bonding of die, which provides for high interconnect density while allowing, for example, logic and memory, to be kept separate. Stacking of multiple die is already in use in some applications and could be refined or there may be methods to process and then add silicon in a sequential 3D process similar to that used to create 3D-NAND flash memories. This has achieved 72 layers in commercial chips (see SK Hynix takes 3D-NAND to 72 layers).

Next: Keep logic and memory separate no more

But whatever schemes are chosen to build multi-billion transistor SoCs at 3nm and beyond are likely to be costly partly because of the Von Neumann architecture that separates memory and processing. There are other computing pradigms that may come to the rescue and Steegan specifically referenced Machine Learning and Quantum Computing. Neural networks have been implemented in software for many years and are now being implemented in GPUs and specialized DSPs for increased energy efficiency. However, Steegan pointed out that IMEC has chosen to use memories such as metal-oxide ReRAM (also known as OxRAM) or MRAM. The variable conductance of ReRAM cells have been used as an analog for synaptic weight in self-learning systems. Steegan said use of memory cells to implement neural networks can provide up to a factor of 100 better efficiency than conventional multibit resolution logic.

Next: Memory field

Steegan then performed a quick tour of the memory field that is littered with old and new candidates. These extend from the logical flip-flops used for latches and registers through high-speed SRAMs and up to magnetic storage. “With four, six or eight transistors the SRAM does not scale well. “The SRAM needs replacement or shrinkage,” said Steegan. The use of vertical FETs may be one way to do that and could achieve a 30 percent area shrink for a 6T SRAM, she said. An alternative is use the smaller non-volatile MRAM if it could be made fast enough. Spin-torque transfer MRAM (STT-MRAM) has switching times of the order of 5ns making it a good candidate for L2 and L3 cache, Steegan said. But there is a form of MRAM that could rival SRAM in speed.

Next: Spin-orbit torque MRAM

The spin-orbit torque MRAM makes use of the spin-Hall effect in a heavy metal layer, such as tungsten, getting switching times down to below 1ns. IMEC has manufactured the first functional SOT-MRAM on a 300mm wafer.

Next: emerging memories for IoT

To get beyond DRAM researchers look at ferroelectric materials to enhance the capacitance of the 1T1C structure and there are also ferroelectric FET structures. Steegan also mentioned IMEC research into conductive bridging RAMs (CBRAMs) based on the movement of metal ions such as silver and copper (see Crossbar ReRAM in production at SMIC). And then there is IMEC’s work on ReRAM based on tantalum oxide and hafnium oxide, which it calls OxRAM implying that the final link in the filamentary connection is made by oxygen vacancies in the insulator between the top and bottom electrodes. This is promising for automotive applications as it appears capable of going to automotive specifications, Steegan said.

Next: Storage class memory

IMEC has also done work on the selector switch for cross-point arrays of so-called storage class memories (SCMs). Reference back the “footprint” slide shows that SCMs are close to flash in performance and are the source of many emerging technologies that seek to win out if and when NAND flash fails to scale. Amongst the candidates are phase change memory (PCM) various forms of ReRAM and ferroelectric transistor memories. Like others such as Intel, IMEC has worked on an ovonic threshold selector. It’s use of germanium-selenide doped with nitrogen is a departure from the more conventional chalcogenide alloy of germanium, antimony and tellurium (GeSbTe) known as GST but has the advantage of getting lose to SCM specification requirements while being thermally stable to 600C.

Steegan covered a number of other topics in an excellent but dense tour of the technological horizon.

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