Coupled with Serial Data Link Analysis (SDLA) software, PCE3 provides a complete solution for verifying transmitter and channel performance of PCIe 3.0 architecture designs and provides support for both the PCIe 3.0 base specification and CEM specification measurements.
The PCIe 3.0 architecture provides a low-cost, high-performance I/O technology that includes a new 128b/130b encoding scheme and a data rate of 8 GT/s, doubling the interconnect bandwidth over the PCIe 2.0 specification. Based on the same board material (FR4) and connectors as previous generations, the PCIe 3.0 architecture represents a far more difficult test challenge, with smaller margins and new jitter measurements required to account for increased signal loss in the channel.
In addition to the new Option PCE3 solution, Tektronix will be showing support for PCI Express Protocol Logic testing with the Tektronix TLA7SA16 and TLA7SA08 Logic Protocol Analyzer modules, bus support software, and probes announced earlier this year that bring PCIe 3.0 logical and protocol testing support to the TLA7000 Series high-performance logic analyzer family.
With 100 GS/s oversampling and up to 20GHz frequency response, the DPO/DSA/MSO70000 Series oscilloscopes deliver the performance and signal fidelity required to meet PCIe 3.0 technology test challenges. Option PCE3 for these instruments accelerates the analysis and validation of PCIe architecture designs and provides the flexibility to check devices for precompliance or perform device characterization or debug in a single software package. Serial Data Link Analysis software enables channel de-convolution, convolution and receiver equalization. DPOJET Jitter and Eye-diagram Analysis software provides jitter, eye-diagram and parametric testing. And the P7520 TriMode Differential Probe is available for validation and debug of chip-to-chip links, including common mode measurements.
Performance validation and stress testing of PCI Express 3.0 receiver designs will also be critical given the large speed increase in the standard. The BERTScope BSA85C provides stressed pattern testing with jitter and interference added to determine effective Bit Error Ratio from new receiver designs.
The BERTScope is complemented by the DPP125B which adds critical pre-emphasis to the stressed pattern, and the CR125A that recovers the embedded clock to allow for eye diagram analysis on the resulting signal. BERTScope provides a true Bit Error Ratio in addition to eye diagram analysis for complete debug of PCIe 3.0 receivers.
These tools integrate with the TLA7SA16 and TLA7SA8 Logic Protocol Analyzer modules to provide complete visibility of PCIe 3.0 physical and logical layers. The combination of the two solutions allow for rapid PCIe 3.0 architecture digital debug and validation, analog validation, compliance testing, and device characterization.