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Tensilica DSP core targets 4k mobile imaging

Tensilica DSP core targets 4k mobile imaging

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By eeNews Europe



The core will, Cadence says, offload its host CPU to minimise energy consumption, and will seek applications in image and video enhancement, stereo and 3D imaging, depth map processing, robotic vision, face detection and authentication, augmented reality, object tracking, object avoidance and advanced noise reduction.

The Tensilica Vision P5 has been specifically configured for applications requiring ultra-high memory and operation parallelism to support complex vision processing at high resolution and high frame rates, Cadence adds, off-loading vision and imaging functions from the main CPU to increase throughput and reduce power.

The core includes an expanded and optimised Instruction Set Architecture (ISA) targeting mobile, automotive advanced driver assistance systems (or ADAS, which includes pedestrian detection, traffic sign recognition, lane tracking, adaptive cruise control, and accident avoidance) and Internet of Things (IoT) vision systems.

Added features in the Tensilica Vision P5 core include:

– 1024-bit-wide memory interface with SuperGather technology for maximum performance on the complex data patterns of vision processing

– Up to four vector ALU operations per cycle, each with up to 64-way data parallelism

– Up to five instructions issued per cycle from 128-bit wide instruction delivering increased operation parallelism

– Enhanced 8-,16- and 32-bit ISA tuned for vision/imaging applications

– Optional 16-way IEEE single-precision vector floating-point processing unit delivering 32 GFLOPs at 1 GHz.

“Imaging algorithms are quickly evolving and becoming much more complex – particularly in object detection, tracking and identification,” notes Chris Rowen, CTO of the IP Group at Cadence. “Additionally, we are seeing a lot more integrated systems with multiple sensor types, feeding even more data in for processing in real time. These highly complex systems are driving us to provide more performance in our DSPs than ever before, at even lower power.”

Cadence also says that the design has improved the ease of software development and porting, with support for integer, fixed-point and floating-point data types and an advanced toolchain with an auto-vectorising C compiler. The software environment also features complete support of standard OpenCV and OpenVX libraries for fast, high-level migration of existing imaging/vision applications with over 800 library functions.

This core is in the lineage of the Tensilica Xtensa architecture, and hardware options with a library of DSP functions and vision/imaging applications, contributed by third parties in Cadence/Tensilica’s ecosystem. The same grouping can support in terms of applications software, emulation and probes, silicon and services. Cadence claims the Xtensa architecture as the second most popular licensable processor architecture, and that more than 2billion cores are being delivered per year.

Cadence; https://ip.cadence.com/ipportfolio/tensilica-ip/image-vision-processing

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