Tensilica processors enter their 11th generation
Enhancements in flexible length instruction extensions (FLIX) for Xtensa LX6 allow for very long instruction word (VLIW) instructions of any length from 4 to 16 bytes, resulting in code size savings of up to 25 percent compared to prior Xtensa versions. This enables local memory and cache size reductions of up to 25 percent for the same performance level.
An option for run-time power-down of portions of cache memories yields up to 75 percent local memory power savings in select operating scenarios with dynamic cache-way control. More efficient data cache block prefetch lowers system power and boosts system performance by speeding functions such as MemCpy by 6.5 times faster and reducing the total number of system bus read operations by up to 23 percent. The processor logic gates used in this 11th generation of processors also features a reduced dynamic switching power by up to 25 percent.
Cadence automates the creation of both hardware and software development tools, allowing customers to create fully optimized processors for many applications in record time and with state-of-the-art software development tools. The Xtensa processor generator technology blends conventional fixed-architecture processor solutions with the innovation potential of Application Specific Instruction-set Processor (ASIP) tools. Every Xtensa processor includes the common core Xtensa instruction set architecture (ISA) that delivers modern, high-performance RISC processor benefits.
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