Terabit-scale secure Ethernet PHY family with port aggregation
Microchip Technology is adding to the META-DX2 Ethernet PHY (physical layer) portfolio by introducing a new family of META-DX2+ PHYs. These are the first devices set to integrate 1.6T (terabits per second) of line-rate end-to-end encryption and port aggregation to maintain the most compact footprint in the transition to 112G PAM4 connectivity for enterprise ethernet switches, security appliances, cloud interconnect routers and optical transport systems.
The new Ethernet PHY family addresses the demand for increased bandwidth and security in network infrastructure driven by growth in hybrid work and geographical distribution of networks is re-defining borderless networking. Led by AI/ML applications, the total port bandwidth for 400G (gigabits per second) and 800G is forecasted to grow at an annual rate of over 50%, according to 650 Group. This dramatic growth is expanding the transition to 112G PAM4 connectivity beyond just cloud data center and telecom service provider switches and routers to enterprise ethernet switching platforms.
“Introduction of four new META-DX2+ Ethernet PHYs demonstrates our commitment to supporting the industry transition to 112G PAM4 connectivity powered by our META-DX retimer and PHY portfolio. In conjunction with our META-DX2L retimer, we now offer a complete chipset for all connectivity needs from retiming, gearboxing, to advanced PHY functionality,” said Babak Samimi, corporate vice president of Microchip’s communications business unit. “By offering both hardware and software footprint compatibility, our customers can leverage architectural designs across their enterprise, datacenter, and service provider switching and routing systems that can offer pay-as-you-need enablement of advanced features including end-to-end security, multi-rate port aggregation, and precision timestamping via software subscription model.”
META-DX2+’s configurable 1.6T datapath architecture outperforms the next near competitors by 2x in total gearbox capacity and hitless 2:1 protection switch mux modes enabled by its unique ShiftIO capability. The flexible XpandIO port aggregation capabilities optimize router/switch port utilization when supporting low-rate traffic.
Also, the devices include IEEE 1588 Class C/D Precision Time Protocol (PTP) support for accurate nanosecond timestamping required for 5G and enterprise business critical services. By offering a portfolio of footprint-compatible retimer and advanced PHYs with encryption options, Microchip enables developers to expand their designs to add MACsec and IPsec based on a common board design and Software Development Kit (SDK).
“As the industry transitions to a 112G PAM4 serial ecosystem for high-density routers and switches, line-rate encryption and efficient use of port capacity becomes increasingly important,” said Alan Weckel, founder and technology analyst at 650 Group, LLC. “Microchip’s META-DX2+ family will play an important role in enabling MACsec and IPsec encryption, optimizing port capacity with port aggregation, and flexibly connecting routing/switching silicon to multi-rate 400G and 800G optics.”
Like the META-DX2L retimer, the new series of META-DX2+ PHYs can be used with Microchip’s PolarFire® FPGAs, the ZL30632 high-performance PLL, oscillators, voltage regulators, and other components that have been pre-validated as a system to help speed designs into production.
Microchip’s second-generation Ethernet PHY SDK for the META-DX2 family lowers development costs with field-proven API libraries and firmware. The SDK supports all META-DX2L and META-DX2+ PHY devices within the product family. Support for the Open Compute Project (OCP) Switch Abstraction Interface (SAI) PHY extensions are included to enable agnostic support of the META-DX2 PHYs within a wide range of Network Operating Systems (NOS) that support SAI.
The META-DX2+ family is expected to sample during the fourth calendar quarter of 2022.