TES launches 3D graphics IP core

TES launches 3D graphics IP core

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By eeNews Europe

D/AVE HD is designed to be fast with powerful functionality and at the same time optimized regarding size and footprint. At 400MHz with 8 parallel pixel pipelines, drawing of 3.2 GPixels/sec is possible. Intelligent data access pre-fetching technology makes the processor independent from memory latencies.
The D/AVE IP-cores are already well established in the embedded market and e.g. used in automotive dashboard controllers as well as in dedicated ASIC- and FPGA-solutions for mobile or industrial applications due to the small footprint.
Targeting modern graphics applications on high resolution displays, Like all other D/AVE cores, D/AVE HD renders sub-pixel accurately and uses the TES Direct-Edge-Antialiasing technology. Sophisticated 2D graphics functionality is complemented by the typically required set of 3D graphics functions including standard APIs.
The D/AVE HD architecture is extremely scalable allowing the optimal configuration of the processor for the target product. E.g. the number of texture units, the number of pixel pipelines and the internal cache and buffer sizes can be configured during the integration of the processor into the target system. Furthermore, different bus widths and bus systems are supported including ARM’s AMBA (APB, AHB, AXI) and Altera’s Avalon. Finally the single clock
architecture eases the integration process.
Besides the highly efficient TES D/AVE HD API also standard graphics APIs like OpenGL ES 1.1 are supported. Optionally – with appropriate configuration of the processor – also the vector graphics API OpenVG can be offered. Due to the built-in hardware multi-threading support, several programs can use the graphics processor simultaneously.
"D/AVE HD is well balanced in functionality, performance and footprint and the scalability allows the optimal configuration of the processor in order to meet the requirements of the target system and application.” says
Thomas Hase, Business Development Manager for Graphics & IP at TES.
The TES team in Hamburg provides support during the configuration and integration of the processor and support for graphics application development can be offered on demand.

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