Test and debug tools for Freescale’s latest Qorivva automotive SoCs

Test and debug tools for Freescale’s latest Qorivva automotive SoCs

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By eeNews Europe

Pre-configured setups of the UDE ensure an uncomplicated first connection as well as fast and reliable programming of the flash memory integrated in various sizes on the Qorivva devices. With help of the UDE’s multicore/multiprogram loader, the relevant program codes and the corresponding debug information can be flexibly assigned to individual cores.

The heterogeneous structure of the SoCs is fully supported; besides the main cores, depending on the type, the devices can contain further programmable units such as a Generic Timer Module (GTM) or a Hardware Security Module (HSM). By core-specific grouping of debugger windows (optionally with automatic fade in and fade out depending on the active core, as well as different colouring) UDE-users are provided with an optimal overview of their complete multicore system in one single consistent user interface.

Control of the diverse cores by the debugger is carried out via the so-called multi-run control function, which enables an almost synchronous start and stop of the various cores by making use of debug logic integrated on the respective chip. In addition, debugging is simplified by the multicore breakpoints newly implemented in the UDE. Using that feature a simultaneously-acting breakpoint for all cores can be set in shared code. Data breakpoints allow the recognition of read and/or write accesses to a variable. A certain expected value can even be optionally taken into account.

In optimisation of the UDE, particular attention was also given to efficient support of all possible trace variants. While data transfer takes place via a conventional parallel port with the types MPC5746C, MPC5748G and MPC574xP, a serial high-speed interface that is based on the Aurora protocol is available for the MPC5746M, MPC577xK, MPC5777M and MPC574xP devices. This offers type-dependent four or two lanes each with 1.25 Gbps data transfer rate, which are processed without limitations by the Aurora trace pod of the Universal Access Device (UAD) 3+. For parallel trace, users can make use of a pod with up to 32-bit recording width.

The various device-specific optimisations of the UDE are particularly valuable when working with Qorivva derivates such as MPC5746M and MPC5777M that were specifically designed for motor controls. In these SoCs, Freescale integrated a few kByte trace memory on the production chip. This trace memory, together with a Signal Processing Unit (SPU) also integrated on the chip, is ideally suited for troubleshooting. The SPU, which can usually only be laboriously programmed at register level, can be simply configured for various measurement tasks with the Universal Emulation Configurator (UEC), which is an option for the UDE from PLS. Besides control of the trace recording, the underlying state machine model also allows the definition of complex breakpoints with sequencer logic.

PLS Programmierbare Logik & Systeme GmbH (Lauta, Germany);

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