Thalia adds parasitic estimation

Thalia adds parasitic estimation

New Products |
By Nick Flaherty

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UK analog IP design tool developer Thalia has added parasitic estimation to its Amalia tool.

Version 24.2 of the Thalia AMALIA tool directly tackles one of the most intricate challenges in semiconductor design—accurate parasitic estimation. This  eliminates this traditional constraint and streamlines the design process by intelligently incorporating extracted parasitics from the source design. These are added during the circuit porting phase to provide estimated parasitics early in the design process.

This improves the accuracy of the ported schematic and reduces the need for multiple post-layout parasitic extraction (PEX) iterations by at least 30%. This is particularly beneficial in high-frequency applications, and smaller process technology nodes, where precision and speed are paramount.

This also streamlines the schematic porting by removing the need for skilled designers to estimate parasitics manually, saving valuable resources and speeding up the design verification process.

“Estimated parasitics in AMALIA is a testament to our commitment to innovation and the tangible benefits it brings to our customers,” said Syed Ahmad, VP of Product Development at Thalia.

AMALIA 24.2 also boosts the IP migration experience with a new design centring assistant feature, and updates to its advanced device mapping. The design centering assistant quickly identifies critical devices that impact performance, facilitating precise adjustments, while the device mapping table now benefits from AI/ML-driven auto device recommendations, ensuring optimal device selection and removing the need for manual work.


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